Design and Implementation of TinyGALS: A Programming Model for ...

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a 1 0,0
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...
a 1 0,0 + a2 0,0 + ... + an 0,0
a 1 0,0 + a2 0,0 + ... + an 0,0 + a0 0,0
Figure 16: Active system state determined by adding the active system state after one non-
interleaved interrupt.
Suppose that module M writes to a global variable. Also suppose that the iteration
of module M is interrupted, and a component in the interrupting source DAG writes to the
same global variable. Then without timing information, we cannot predict the final value of
the global variable at the end of the iteration. (Note that when read, a global variable always
contains the same value throughout an entire module iteration). As currently defined, the
state of the system after the iteration of module M is interrupted by one or more interrupts is
highly dependent on the time at which the components in M write to the global variable(s).
There are several possible alternatives eliminate this source of nondeterminacy.
Solution 1 Allow only one writer for each TinyGUYS global variable.
Solution 2 Allow multiple writers, but only if they can never write at the same time. That
is, if a component in a triggered DAG writes to a TinyGUYS global variable,
no component in any source DAG can be a writer (but components in other trig-
gered DAGs are allowed since they cannot execute at the same time). Likewise,
if a component in a source DAG writes to a TinyGUYS global variable then no
component in any triggered DAG can be a writer. Components in other source
DAGs are only allowed to write if all interrupts are masked.
Solution 3 Delay writes to a TinyGUYS global variable by an iterating module until the
end of the iteration.
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