Design and Implementation of TinyGALS: A Programming Model for ...
Design and Implementation of TinyGALS: A Programming Model for ...
Design and Implementation of TinyGALS: A Programming Model for ...
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as in a normal method call. 8 The graph <strong>of</strong> components <strong>and</strong> links between them is an ab-<br />
straction <strong>of</strong> the call graph <strong>of</strong> methods within a module, where the methods associated with<br />
a single component are grouped together.<br />
The execution <strong>of</strong> modules is controlled by a scheduler in the <strong>TinyGALS</strong> runtime sys-<br />
tem. There are two cases in which a module M may begin execution: (1) a triggered<br />
component is activated, or (2) a source component is activated. In the first case, the sched-<br />
uler activates the component attached to an input port <strong>of</strong> M in response to an event sent<br />
to M by another module. In the second case, M contains a source component which has<br />
received a hardware interrupt. Notice that in this case, M may be interrupting the execution<br />
<strong>of</strong> another module. A module is considered to be finished executing when the components<br />
inside <strong>of</strong> it have finished executing <strong>and</strong> control has returned to the scheduler.<br />
As discussed in the previous section, preemption <strong>of</strong> the normal thread <strong>of</strong> execution by<br />
an interrupt may lead to reentrancy problems. There<strong>for</strong>e, we must place some restrictions<br />
on what configurations <strong>of</strong> components within a module are allowed.<br />
Cycles within modules (between components) are not allowed, otherwise reentrant<br />
components are required. 9 There<strong>for</strong>e, any valid configurations <strong>of</strong> components within a<br />
module can be modeled as a directed acyclic graph (DAG). A source DAG in a module<br />
M is <strong>for</strong>med by starting with a source component C in M <strong>and</strong> following all <strong>for</strong>ward links<br />
between C <strong>and</strong> other components in M. Figure 7 shows an example <strong>of</strong> a source DAG in-<br />
side <strong>of</strong> a module. A triggered DAG in a module M is <strong>for</strong>med by starting with a triggered<br />
component C in M <strong>and</strong> following all <strong>for</strong>ward links between C <strong>and</strong> other components in M.<br />
Figure 8 shows an example <strong>of</strong> a triggered DAG inside <strong>of</strong> a module.<br />
In general, within a module, source DAGs <strong>and</strong> triggered DAGs must be not be con-<br />
nected. In Figure 9, the source DAG (C1, C3) is connected to the triggered DAG (C2,<br />
C3). Suppose C2 is triggered by an event on the input port <strong>of</strong> M <strong>and</strong> calls C3. Reentrancy<br />
live.<br />
8 In TinyOS, the return value indicates whether the comm<strong>and</strong> completed successfully or not.<br />
9 Recursion within components is allowed. However, the recursion must be bounded <strong>for</strong> the system to be<br />
16
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