Design and Implementation of TinyGALS: A Programming Model for ...

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4 Code Generation 31 4.1 Links and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2 System Initialization and Start of Execution . . . . . . . . . . . . . . . . . 33 4.3 Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4 TinyGUYS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.5 Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.6 Memory Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5 Example 38 6 Related Work 42 6.1 TinyOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.2 Port-Based Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3 Click . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.4 Ptolemy and CI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.5 Timed Multitasking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7 Conclusion 57 7.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ii
8 Acknowledgements 60 iii
Page 1: Design and Implementation of TinyGA
Page 5: Contents 1 Introduction 1 2 The Tin
Page 10 and 11: does not require synchronization, w
Page 12 and 13: integrate subsystems that share a c
Page 14 and 15: 2 The TinyGALS Programming Model Ti
Page 16 and 17: 2.2.1 TinyGALS Components Component
Page 18 and 19: Component implementation for COUNTE
Page 20 and 21: Module definition for leds. include
Page 22 and 23: uns in a single thread of execution
Page 24 and 25: as in a normal method call. 8 The g
Page 26 and 27: nondeterministic component firing o
Page 28 and 29: module. Tokens are placed in input
Page 30 and 31: Application def. include modules{ A
Page 32 and 33: 1. The values of all internal varia
Page 34 and 35: Conditions for well-formedness Here
Page 36 and 37: Determinacy of a system without glo
Page 38 and 39: I0 q0 I1 I2 In a 1 0,0 a 1 0,0 + a2
Page 40 and 41: app_init() app_start() statevar_PAR
Page 42 and 43: the same name as the output port. T
Page 44 and 45: if there is an event in the global
Page 46 and 47: 5 Example The TinyGALS programming
Page 48 and 49: the motes as three separate modules
Page 50 and 51: Table 4: Code size comparison of BL
Page 52 and 53: gered modules in TinyGALS and tasks
Page 54 and 55: critical section to maintain data i
Page 56 and 57:
and a pull port is illegal. Every p
Page 58 and 59:
Poll packet from receive DMA ring P
Page 60 and 61:
Click router thread TinyGALS thread
Page 62 and 63:
unlike Click, the TinyGALS model do
Page 64 and 65:
6.5 Timed Multitasking Timed multit
Page 66 and 67:
quiescent system state to the next
Page 68 and 69:
8 Acknowledgements I wish to thank
Page 70 and 71:
[11] S. S. Bhattacharyya, E. Cheong
Page 72 and 73:
[31] T. J. Mowbray, W. A. Ruh, and
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