Design and Implementation of TinyGALS: A Programming Model for ...

Conditions for well-formedness Here, we summarize the conditions for well-formedness
of a system, as discussed in Section 2.3.
1. Source (interrupt-driven) components must only have outputs, they may not have
inputs. In other words, source components may not also be triggered components
(triggered by an event on a module input port) nor called components (called by
other components).
2. Cycles among components within a module are not allowed, but loops around mod-
ules are allowed.
3. Within a module, component source DAGs and triggered DAGs must be discon-
nected.
4. Within a module, component source DAGs must not be connected to other source
DAGs, but triggered DAGs may be connected to other triggered DAGs. We assume
that an interrupt whose handler is running is masked, but other interrupts are not
masked.
5. Within a module, outgoing component methods may be associated with either one
method of another component, or with one or more module output ports.
6. Within a module, module input ports may be associated with either one method of a
single component, or with one or more module output ports.
3.1 Determinacy
Given the definitions in the previous section, we first discuss determinism of a TinyGALS
system in the case of a single interrupt when in a quiescent state. We then discuss deter-
minism for one or more interrupts during module iteration in the cases where there are no
global variables and when there are global variables.
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