Design and Implementation of TinyGALS: A Programming Model for ...

More documents

Recommendations

Info

8 Acknowledgements I wish to thank Jie Liu for his invaluable guidance in the development of this research project. Judy Liebman implemented the target detection and tracking examples on the motes. Discussions with Jörn Janneck and John Reekie provided the basis for the section on determinacy. Figure 24 is based on a discussion with Xiaojun Liu. Figures 21, 22, 23 were generated from files in the Click 1.3pre1 release [1] and reprinted with permission from Ed- die Kohler, who also provided clarifications via email on how connections are established in the Click architecture. I would like to thank Feng Zhao and others at PARC for a productive and memo- rable summer internship. Much appreciation goes to Jörn Janneck, Jie Liu, and Roberto Passerone for reviewing this report and previous presentations on TinyGALS. I would also like to thank the Ptolemy group for feedback on TinyGALS, and the NEST group at UC Berkeley for creating TinyOS and the mote platform. 60
References [1] The Click modular router project. http://www.pdos.lcs.mit.edu/click/. [2] Echidna: A real-time operating system to support reconfig- urable software on microcontrollers and digital signal processors. http://www.enee.umd.edu/serts/research/echidna. [3] Mescal - modern embedded systems: Compilers, architectures, and languages. http://www.gigascale.org/mescal/. [4] The Ptolemy project. http://ptolemy.eecs.berkeley.edu. [5] TinyOS: a component-based OS for the networked sensor regime. http://webs.cs.berkeley.edu/tos/. [6] G. R. Andrews. Concurrent Programming: Principles and Practice. Addison-Wesley Publishing Company, 1991. [7] F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni- Vincentelli, E. M. Sentovich, and K. Suzuki. Synthesis of software programs for embedded control applications. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(6):834–849, June 1999. [8] A. Benveniste, B. Caillaud, and P. L. Guernic. From synchrony to asynchrony. In J. C. Baeten and S. Mauw, editors, 10th International Conference on Concurrency Theory (CONCUR’99), volume 1664 of Lecture Notes in Computer Science, pages 162–177. Springer-Verlag, August 1999. [9] A. Benveniste, P. Caspi, S. A. Edwards, N. Halbwachs, P. L. Guernic, and R. de Si- mone. The synchronous languages 12 years later. Proceedings of the IEEE, 91(1):64– 83, January 2003. [10] G. Berry. The foundations of Esterel. In G. Plotkin, C. Stirling, and M. Tofte, editors, Proof, Language, and Interaction: Essays in Honour of Robin Milner, pages 425– 454. MIT Press, 2000. 61
Page 1:
Design and Implementation of TinyGA
Page 5 and 6:
Contents 1 Introduction 1 2 The Tin
Page 7:
8 Acknowledgements 60 iii
Page 10 and 11:
does not require synchronization, w
Page 12 and 13:
integrate subsystems that share a c
Page 14 and 15:
2 The TinyGALS Programming Model Ti
Page 16 and 17:
2.2.1 TinyGALS Components Component
Page 18 and 19: Component implementation for COUNTE
Page 20 and 21: Module definition for leds. include
Page 22 and 23: uns in a single thread of execution
Page 24 and 25: as in a normal method call. 8 The g
Page 26 and 27: nondeterministic component firing o
Page 28 and 29: module. Tokens are placed in input
Page 30 and 31: Application def. include modules{ A
Page 32 and 33: 1. The values of all internal varia
Page 34 and 35: Conditions for well-formedness Here
Page 36 and 37: Determinacy of a system without glo
Page 38 and 39: I0 q0 I1 I2 In a 1 0,0 a 1 0,0 + a2
Page 40 and 41: app_init() app_start() statevar_PAR
Page 42 and 43: the same name as the output port. T
Page 44 and 45: if there is an event in the global
Page 46 and 47: 5 Example The TinyGALS programming
Page 48 and 49: the motes as three separate modules
Page 50 and 51: Table 4: Code size comparison of BL
Page 52 and 53: gered modules in TinyGALS and tasks
Page 54 and 55: critical section to maintain data i
Page 56 and 57: and a pull port is illegal. Every p
Page 58 and 59: Poll packet from receive DMA ring P
Page 60 and 61: Click router thread TinyGALS thread
Page 62 and 63: unlike Click, the TinyGALS model do
Page 64 and 65: 6.5 Timed Multitasking Timed multit
Page 66 and 67: quiescent system state to the next
Page 70 and 71: [11] S. S. Bhattacharyya, E. Cheong
Page 72 and 73: [31] T. J. Mowbray, W. A. Ruh, and
show all

Design and Implementation of TinyGALS: A Programming Model for ...

Create successful ePaper yourself

Delete template?

Save as template?