Design and Implementation of TinyGALS: A Programming Model for ...

Determinacy of a system without global variables. We will first examine the case
where there are no TinyGUYS global variables.
Let us consider a module M that contains a component C which produces events on
the outports of M. Suppose the iteration of module M is interrupted one or more times.
Since source DAGs must not be connected to triggered DAGs, the interrupt(s) cannot cause
the production of events on outports of M that would be used in the case of a normal
uninterrupted iteration. However, the interrupt(s) may cause insertion of events into other
module inport queues, and hence insertions into the global event queue. Depending on the
relative timing between the interrupts and the production of events by C at outports of M,
the order of events in the global event queue may not be consistent between multiple runs
of the system if the same interrupts occur during the same module iteration, but at slightly
different times. This is a source of non-determinacy.
If we wish to reduce the non-determinacy in the system, a partial solution is to delay
producing outputs from the module being iterated until the end of its iteration. If we know
the order of interrupts, then we can predict the state of the system after a single module
iteration even if it is interrupted one or more times. Figure 14 shows a system execution in
which a single module iteration is interrupted by multiple interrupts. In our notation, a i j,k
refers to an active system state after an interrupt Ii starting from quiescent state q j and after
module iteration mk. In Figure 14, the superscript in ax j,k is a shorthand for the sequence of
interrupts I0,I1,I2,...,In.
I0
q0
I1I2 In
...
a x 0,0
a x 0,1
...
a x 0,n
Figure 14: One or more interrupts where modules have delayed output.
In order to determine the value of active system state ax j,k , we can “add” the combined
system states. Suppose active state a1 0,0 would be the next state after an iteration of the
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q1