AVR Instruction Set Nomenclature: Status Register (SREG ...

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Example: Words: 1 (2 bytes) Cycles: 2 122 clr r27 ; Clear X high byte ldi r26,$60 ; Set X low byte to $60 st X+,r0 ; Store r0 in data space loc. $60(X post inc) st X,r1 ; Store r1 in data space loc. $61 ldi r26,$63 ; Set X low byte to $63 st X,r2 ; Store r2 in data space loc. $63 st -X,r3 ; Store r3 in data space loc. $62(X pre dec) Instruction Set
ST (STD) - Store Indirect From Register to data space using Index Y Instruction Set Description: Stores one byte indirect with or without displacement from a register to data space. For parts with SRAM, the data space consists of the register file, I/O memory and internal SRAM (and external SRAM if applicable). For parts without SRAM, the data space consists of the register file only. The EEPROM has a separate address space. The data location is pointed to by the Y (16 bits) pointer register in the register file. Memory access is limited to the current data segment of 64K bytes. To access another data segment in devices with more than 64K bytes data space, the RAMPY in register in the I/O area has to be changed. The Y pointer register can either be left unchanged by the operation, or it can be post-incremented or pre-decremented. These features are especially suited for accessing arrays, tables, and stack pointer usage of the Y pointer register. Note that only the low byte of the Y pointer is updated in devices with no more than 256 bytes data space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other purposes. The RAMPY register in the I/O area is updated in parts with more than 64K bytes data space, and the displacement is added to the entire 24-bit address on such devices. The result of these combinations is undefined: ST Y+, r28 ST Y+, r29 ST -Y, r28 ST -Y, r29 Using the Y pointer: Operation: Comment: (i) (Y) ← Rr Y: Unchanged (ii) (Y) ← Rr Y ← Y+1 Y: Post incremented (iii) Y ← Y - 1 (Y) ← Rr Y: Pre decremented (iiii) (Y+q) ← Rr Y: Unchanged, q: Displacement Syntax: Operands: Program Counter: (i) ST Y, Rr 0 ≤ r ≤ 31 PC ← PC + 1 (ii) ST Y+, Rr 0 ≤ r ≤ 31 PC ← PC + 1 (iii) ST -Y, Rr 0 ≤ r ≤ 31 PC ← PC + 1 (iiii) STD Y+q, Rr 0 ≤ r ≤ 31, 0 ≤ q ≤ 63 PC ← PC + 1 16-bit Opcode: (i) 1000 001r rrrr 1000 (ii) 1001 001r rrrr 1001 (iii) 1001 001r rrrr 1010 (iiii) 10q0 qq1r rrrr 1qqq Status Register (SREG) and Boolean Formula: I T H S V N Z C - - - - - - - - 123
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Instruction Set Nomenclature: Statu
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Conditional Branch Summary Instruct
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Instruction Set Summary (Continued)
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Instruction Set Summary (Continued)
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ADC - Add with Carry Description: A
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ADIW - Add Immediate to Word Instru
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ANDI - Logical AND with Immediate I
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BCLR - Bit Clear in SREG Descriptio
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BRBC - Branch if Bit in SREG is Cle
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BRCC - Branch if Carry Cleared Inst
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BREQ - Branch if Equal Instruction
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BRHC - Branch if Half Carry Flag is
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BRID - Branch if Global Interrupt i
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BRLO - Branch if Lower (Unsigned) I
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BRMI - Branch if Minus Instruction
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BRPL - Branch if Plus Instruction S
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BRTC - Branch if the T Flag is Clea
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BRVC - Branch if Overflow Cleared I
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BSET - Bit Set in SREG Description:
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CALL - Long Call to a Subroutine In
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CBR - Clear Bits in Register Instru
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CLH - Clear Half Carry Flag Descrip
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CLN - Clear Negative Flag Descripti
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CLS - Clear Signed Flag Description
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CLV - Clear Overflow Flag Descripti
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COM - One’s Complement Descriptio
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CPC - Compare with Carry Instructio
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CPSE - Compare Skip if Equal Instru
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EICALL - Extended Indirect Call to
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ELPM - Extended Load Program Memory
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ESPM - Extended Store Program Memor
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FMUL - Fractional Multiply Unsigned
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FMULSU - Fractional Multiply Signed
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IJMP - Indirect Jump Instruction Se
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INC - Increment Instruction Set Des
Page 71 and 72: LD - Load Indirect from data space
Page 73 and 74: LD (LDD) - Load Indirect from data
Page 75 and 76: LD (LDD) - Load Indirect From data
Page 77 and 78: LDI - Load Immediate Description: L
Page 79 and 80: LPM - Load Program Memory Instructi
Page 81 and 82: LSR - Logical Shift Right Instructi
Page 83 and 84: MOVW - Copy Register Word Instructi
Page 85 and 86: MULS - Multiply Signed Description:
Page 87 and 88: NEG - Two’s Complement Descriptio
Page 89 and 90: OR - Logical OR Instruction Set Des
Page 91 and 92: OUT - Store Register to I/O Locatio
Page 93 and 94: PUSH - Push Register on Stack Instr
Page 95 and 96: RET - Return from Subroutine Instru
Page 97 and 98: RJMP - Relative Jump Instruction Se
Page 99 and 100: ROR - Rotate Right through Carry In
Page 101 and 102: SBC - Subtract with Carry Instructi
Page 103 and 104: SBI - Set Bit in I/O Register Instr
Page 105 and 106: SBIS - Skip if Bit in I/O Register
Page 107 and 108: SBR - Set Bits in Register Instruct
Page 109 and 110: SBRS - Skip if Bit in Register is S
Page 111 and 112: SEH - Set Half Carry Flag Descripti
Page 113 and 114: SEN - Set Negative Flag Description
Page 115 and 116: SES - Set Signed Flag Description:
Page 117 and 118: SEV - Set Overflow Flag Description
Page 119 and 120: SLEEP Description: This instruction
Page 121: ST - Store Indirect From Register t
Page 125 and 126: ST (STD) - Store Indirect From Regi
Page 127 and 128: STS - Store Direct to data space In
Page 129 and 130: SUBI - Subtract Immediate Instructi
Page 131 and 132: TST - Test for Zero or Minus Instru
Page 133: Atmel Headquarters Atmel Operations
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AVR Instruction Set Nomenclature: Status Register (SREG ...

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