AVR Instruction Set Nomenclature: Status Register (SREG ...

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I/O Registers RAMPX, RAMPY, RAMPZ Registers concatenated with the X, Y and Z registers enabling indirect addressing of the whole data space on MCUs with more than 64K bytes data space, and constant data fetch on MCUs with more than 64K bytes program space. RAMPD Register concatenated with the Z register enabling direct addressing of the whole data space on MCUs with more than 64K bytes data space. EIND Register concatenated with the instruction word enabling indirect jump and call to the whole program space on MCUs with more than 64K bytes program space. Stack STACK: Stack for return address and pushed registers SP: Stack Pointer to STACK Flags ⇔: Flag affected by instruction 0: Flag cleared by instruction 1: Flag set by instruction -: Flag not affected by instruction 2 Instruction Set
Conditional Branch Summary Instruction Set Test Boolean Mnemonic Complementary Boolean Mnemonic Comment Rd > Rr Z•(N ⊕ V) = 0 BRLT (1) Rd ≤ Rr Z+(N ⊕ V) = 1 BRGE* Signed Rd ≥ Rr (N ⊕ V) = 0 BRGE Rd < Rr (N ⊕ V) = 1 BRLT Signed Rd = Rr Z = 1 BREQ Rd ≠ Rr Z = 0 BRNE Signed Rd ≤ Rr Z+(N ⊕ V) = 1 BRGE (1) Rd > Rr Z•(N ⊕ V) = 0 BRLT* Signed Rd < Rr (N ⊕ V) = 1 BRLT Rd ≥ Rr (N ⊕ V) = 0 BRGE Signed Rd > Rr C + Z = 0 BRLO (1) Rd ≤ Rr C + Z = 1 BRSH* Unsigned Rd ≥ Rr C = 0 BRSH/BRCC Rd < Rr C = 1 BRLO/BRCS Unsigned Rd = Rr Z = 1 BREQ Rd ≠ Rr Z = 0 BRNE Unsigned Rd ≤ Rr C + Z = 1 BRSH (1) Rd > Rr C + Z = 0 BRLO* Unsigned Rd < Rr C = 1 BRLO/BRCS Rd ≥ Rr C = 0 BRSH/BRCC Unsigned Carry C = 1 BRCS No carry C = 0 BRCC Simple Negative N = 1 BRMI Positive N = 0 BRPL Simple Overflow V = 1 BRVS No overflow V = 0 BRVC Simple Zero Z = 1 BREQ Not zero Z = 0 BRNE Simple Note: 1. Interchange Rd and Rr in the operation before the test. i.e. CP Rd,Rr → CP Rr,Rd 3
Page 1: Instruction Set Nomenclature: Statu
Page 5 and 6: Instruction Set Summary (Continued)
Page 7 and 8: Instruction Set Summary (Continued)
Page 9 and 10: ADC - Add with Carry Description: A
Page 11 and 12: ADIW - Add Immediate to Word Instru
Page 13 and 14: ANDI - Logical AND with Immediate I
Page 15 and 16: BCLR - Bit Clear in SREG Descriptio
Page 17 and 18: BRBC - Branch if Bit in SREG is Cle
Page 19 and 20: BRCC - Branch if Carry Cleared Inst
Page 21 and 22: BREQ - Branch if Equal Instruction
Page 23 and 24: BRHC - Branch if Half Carry Flag is
Page 25 and 26: BRID - Branch if Global Interrupt i
Page 27 and 28: BRLO - Branch if Lower (Unsigned) I
Page 29 and 30: BRMI - Branch if Minus Instruction
Page 31 and 32: BRPL - Branch if Plus Instruction S
Page 33 and 34: BRTC - Branch if the T Flag is Clea
Page 35 and 36: BRVC - Branch if Overflow Cleared I
Page 37 and 38: BSET - Bit Set in SREG Description:
Page 39 and 40: CALL - Long Call to a Subroutine In
Page 41 and 42: CBR - Clear Bits in Register Instru
Page 43 and 44: CLH - Clear Half Carry Flag Descrip
Page 45 and 46: CLN - Clear Negative Flag Descripti
Page 47 and 48: CLS - Clear Signed Flag Description
Page 49 and 50: CLV - Clear Overflow Flag Descripti
Page 51 and 52: COM - One’s Complement Descriptio
Page 53 and 54:
CPC - Compare with Carry Instructio
Page 55 and 56:
CPSE - Compare Skip if Equal Instru
Page 57 and 58:
EICALL - Extended Indirect Call to
Page 59 and 60:
ELPM - Extended Load Program Memory
Page 61 and 62:
ESPM - Extended Store Program Memor
Page 63 and 64:
FMUL - Fractional Multiply Unsigned
Page 65 and 66:
FMULSU - Fractional Multiply Signed
Page 67 and 68:
IJMP - Indirect Jump Instruction Se
Page 69 and 70:
INC - Increment Instruction Set Des
Page 71 and 72:
LD - Load Indirect from data space
Page 73 and 74:
LD (LDD) - Load Indirect from data
Page 75 and 76:
LD (LDD) - Load Indirect From data
Page 77 and 78:
LDI - Load Immediate Description: L
Page 79 and 80:
LPM - Load Program Memory Instructi
Page 81 and 82:
LSR - Logical Shift Right Instructi
Page 83 and 84:
MOVW - Copy Register Word Instructi
Page 85 and 86:
MULS - Multiply Signed Description:
Page 87 and 88:
NEG - Two’s Complement Descriptio
Page 89 and 90:
OR - Logical OR Instruction Set Des
Page 91 and 92:
OUT - Store Register to I/O Locatio
Page 93 and 94:
PUSH - Push Register on Stack Instr
Page 95 and 96:
RET - Return from Subroutine Instru
Page 97 and 98:
RJMP - Relative Jump Instruction Se
Page 99 and 100:
ROR - Rotate Right through Carry In
Page 101 and 102:
SBC - Subtract with Carry Instructi
Page 103 and 104:
SBI - Set Bit in I/O Register Instr
Page 105 and 106:
SBIS - Skip if Bit in I/O Register
Page 107 and 108:
SBR - Set Bits in Register Instruct
Page 109 and 110:
SBRS - Skip if Bit in Register is S
Page 111 and 112:
SEH - Set Half Carry Flag Descripti
Page 113 and 114:
SEN - Set Negative Flag Description
Page 115 and 116:
SES - Set Signed Flag Description:
Page 117 and 118:
SEV - Set Overflow Flag Description
Page 119 and 120:
SLEEP Description: This instruction
Page 121 and 122:
ST - Store Indirect From Register t
Page 123 and 124:
ST (STD) - Store Indirect From Regi
Page 125 and 126:
ST (STD) - Store Indirect From Regi
Page 127 and 128:
STS - Store Direct to data space In
Page 129 and 130:
SUBI - Subtract Immediate Instructi
Page 131 and 132:
TST - Test for Zero or Minus Instru
Page 133:
Atmel Headquarters Atmel Operations
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AVR Instruction Set Nomenclature: Status Register (SREG ...

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