AVR Instruction Set Nomenclature: Status Register (SREG ...

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LDS - Load Direct from data space Description: Loads one byte from the data space to a register. For parts with SRAM, the data space consists of the register file, I/O memory and internal SRAM (and external SRAM if applicable). For parts without SRAM, the data space consists of the register file only. The EEPROM has a separate address space. A 16-bit address must be supplied. Memory access is limited to the current data segment of 64K bytes. The LDS instruction uses the RAMPD register to access memory above 64K bytes. To access another data segment in devices with more than 64K bytes data space, the RAMPD in register in the I/O area has to be changed. Operation: (i) Rd ← (k) Syntax: Operands: Program Counter: (i) LDS Rd,k 0 ≤ d ≤ 31, 0 ≤ k ≤ 65535 PC ← PC + 2 78 32-bit Opcode: Status Register (SREG) and Boolean Formula: Example: 1001 000d dddd 0000 kkkk kkkk kkkk kkkk I T H S V N Z C - - - - - - - - lds r2,$FF00 ; Load r2 with the contents of data space location $FF00 add r2,r1 ; add r1 to r2 sts $FF00,r2 ; Write back Words: 2 (4 bytes) Cycles: 2 Instruction Set
LPM - Load Program Memory Instruction Set Description: Loads one byte pointed to by the Z register into the destination register Rd. This instruction features a 100% space effective constant initialization or constant data fetch. The program memory is organized in 16 bit words and the least significant bit of the Z pointer selects either low byte (0) or high byte (1). This instruction can address the first 64K bytes (32K words) of program memory. The Z pointer register can either be left unchanged by the operation, or it can be incremented. The incrementation does not apply to the RAMPZ register. The result of these combinations is undefined: LPM r30, Z+ LPM r31, Z+ Operation: Comment: (i) R0 ← (Z) Z: Unchanged, R0 implied destination register (ii) Rd ← (Z) Z: Unchanged (iii) Rd ← (Z) Z ← Z + 1 Z: Post incremented Syntax: Operands: Program Counter: (i) LPM None, R0 implied PC ← PC + 1 (ii) LPM Rd, Z 0 ≤ d ≤ 31 PC ← PC + 1 (iii) LPM Rd, Z+ 0 ≤ d ≤ 31 PC ← PC + 1 16-bit Opcode: Status Register (SREG) and Boolean Formula: Example: (i) 1001 0101 1100 1000 (ii) 1001 000d dddd 0100 (iii) 1001 000d dddd 0101 I T H S V N Z C - - - - - - - - clr r31 ; Clear Z high byte ldi r30,$F0 ; Set Z low byte lpm ; Load constant from program ; memory pointed to by Z (r31:r30) Words: 1 (2 bytes) Cycles: 3 79
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Instruction Set Nomenclature: Statu
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Conditional Branch Summary Instruct
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Instruction Set Summary (Continued)
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Instruction Set Summary (Continued)
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ADC - Add with Carry Description: A
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ADIW - Add Immediate to Word Instru
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ANDI - Logical AND with Immediate I
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BCLR - Bit Clear in SREG Descriptio
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BRBC - Branch if Bit in SREG is Cle
Page 19 and 20:
BRCC - Branch if Carry Cleared Inst
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BREQ - Branch if Equal Instruction
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BRHC - Branch if Half Carry Flag is
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BRID - Branch if Global Interrupt i
Page 27 and 28: BRLO - Branch if Lower (Unsigned) I
Page 29 and 30: BRMI - Branch if Minus Instruction
Page 31 and 32: BRPL - Branch if Plus Instruction S
Page 33 and 34: BRTC - Branch if the T Flag is Clea
Page 35 and 36: BRVC - Branch if Overflow Cleared I
Page 37 and 38: BSET - Bit Set in SREG Description:
Page 39 and 40: CALL - Long Call to a Subroutine In
Page 41 and 42: CBR - Clear Bits in Register Instru
Page 43 and 44: CLH - Clear Half Carry Flag Descrip
Page 45 and 46: CLN - Clear Negative Flag Descripti
Page 47 and 48: CLS - Clear Signed Flag Description
Page 49 and 50: CLV - Clear Overflow Flag Descripti
Page 51 and 52: COM - One’s Complement Descriptio
Page 53 and 54: CPC - Compare with Carry Instructio
Page 55 and 56: CPSE - Compare Skip if Equal Instru
Page 57 and 58: EICALL - Extended Indirect Call to
Page 59 and 60: ELPM - Extended Load Program Memory
Page 61 and 62: ESPM - Extended Store Program Memor
Page 63 and 64: FMUL - Fractional Multiply Unsigned
Page 65 and 66: FMULSU - Fractional Multiply Signed
Page 67 and 68: IJMP - Indirect Jump Instruction Se
Page 69 and 70: INC - Increment Instruction Set Des
Page 71 and 72: LD - Load Indirect from data space
Page 73 and 74: LD (LDD) - Load Indirect from data
Page 75 and 76: LD (LDD) - Load Indirect From data
Page 77: LDI - Load Immediate Description: L
Page 81 and 82: LSR - Logical Shift Right Instructi
Page 83 and 84: MOVW - Copy Register Word Instructi
Page 85 and 86: MULS - Multiply Signed Description:
Page 87 and 88: NEG - Two’s Complement Descriptio
Page 89 and 90: OR - Logical OR Instruction Set Des
Page 91 and 92: OUT - Store Register to I/O Locatio
Page 93 and 94: PUSH - Push Register on Stack Instr
Page 95 and 96: RET - Return from Subroutine Instru
Page 97 and 98: RJMP - Relative Jump Instruction Se
Page 99 and 100: ROR - Rotate Right through Carry In
Page 101 and 102: SBC - Subtract with Carry Instructi
Page 103 and 104: SBI - Set Bit in I/O Register Instr
Page 105 and 106: SBIS - Skip if Bit in I/O Register
Page 107 and 108: SBR - Set Bits in Register Instruct
Page 109 and 110: SBRS - Skip if Bit in Register is S
Page 111 and 112: SEH - Set Half Carry Flag Descripti
Page 113 and 114: SEN - Set Negative Flag Description
Page 115 and 116: SES - Set Signed Flag Description:
Page 117 and 118: SEV - Set Overflow Flag Description
Page 119 and 120: SLEEP Description: This instruction
Page 121 and 122: ST - Store Indirect From Register t
Page 123 and 124: ST (STD) - Store Indirect From Regi
Page 125 and 126: ST (STD) - Store Indirect From Regi
Page 127 and 128: STS - Store Direct to data space In
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SUBI - Subtract Immediate Instructi
Page 131 and 132:
TST - Test for Zero or Minus Instru
Page 133:
Atmel Headquarters Atmel Operations
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AVR Instruction Set Nomenclature: Status Register (SREG ...

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