AVR Instruction Set Nomenclature: Status Register (SREG ...

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JMP - Jump Description: Jump to an address within the entire 4M (words) program memory. See also RJMP. Operation: (i) PC ← k Syntax: Operands: Program Counter: Stack: (i) JMP k 0 ≤ k < 4M PC ← k Unchanged 70 32-bit Opcode: Status Register (SREG) and Boolean Formula: Example: 1001 010k kkkk 110k kkkk kkkk kkkk kkkk I T H S V N Z C - - - - - - - - mov r1,r0 ; Copy r0 to r1 jmp ... farplc ; Unconditional jump farplc: nop ; Jump destination (do nothing) Words: 2 (4 bytes) Cycles: 3 Instruction Set
LD - Load Indirect from data space to Register using Index X Instruction Set Description: Loads one byte indirect from the data space to a register. For parts with SRAM, the data space consists of the register file, I/O memory and internal SRAM (and external SRAM if applicable). For parts without SRAM, the data space consists of the register file only. The EEPROM has a separate address space. The data location is pointed to by the X (16 bits) pointer register in the register file. Memory access is limited to the current data segment of 64K bytes. To access another data segment in devices with more than 64K bytes data space, the RAMPX in register in the I/O area has to be changed. The X pointer register can either be left unchanged by the operation, or it can be post-incremented or pre-decremented. These features are especially suited for accessing arrays, tables, and stack pointer usage of the X pointer register. Note that only the low byte of the X pointer is updated in devices with no more than 256 bytes data space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other purposes. The RAMPX register in the I/O area is updated in parts with more than 64K bytes data space. The result of these combinations is undefined: LD r26, X+ LD r27, X+ LD r26, -X LD r27, -X Using the X pointer: Operation: Comment: (i) Rd ← (X) X: Unchanged (ii) Rd ← (X) X ← X + 1 X: Post incremented (iii) X ← X - 1 Rd ← (X) X: Pre decremented Syntax: Operands: Program Counter: (i) LD Rd, X 0 ≤ d ≤ 31 PC ← PC + 1 (ii) LD Rd, X+ 0 ≤ d ≤ 31 PC ← PC + 1 (iii) LD Rd, -X 0 ≤ d ≤ 31 PC ← PC + 1 16-bit Opcode: (i) 1001 000d dddd 1100 (ii) 1001 000d dddd 1101 (iii) 1001 000d dddd 1110 Status Register (SREG) and Boolean Formula: I T H S V N Z C - - - - - - - - 71
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Instruction Set Nomenclature: Statu
Page 3 and 4:
Conditional Branch Summary Instruct
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Instruction Set Summary (Continued)
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Instruction Set Summary (Continued)
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ADC - Add with Carry Description: A
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ADIW - Add Immediate to Word Instru
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ANDI - Logical AND with Immediate I
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BCLR - Bit Clear in SREG Descriptio
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BRBC - Branch if Bit in SREG is Cle
Page 19 and 20: BRCC - Branch if Carry Cleared Inst
Page 21 and 22: BREQ - Branch if Equal Instruction
Page 23 and 24: BRHC - Branch if Half Carry Flag is
Page 25 and 26: BRID - Branch if Global Interrupt i
Page 27 and 28: BRLO - Branch if Lower (Unsigned) I
Page 29 and 30: BRMI - Branch if Minus Instruction
Page 31 and 32: BRPL - Branch if Plus Instruction S
Page 33 and 34: BRTC - Branch if the T Flag is Clea
Page 35 and 36: BRVC - Branch if Overflow Cleared I
Page 37 and 38: BSET - Bit Set in SREG Description:
Page 39 and 40: CALL - Long Call to a Subroutine In
Page 41 and 42: CBR - Clear Bits in Register Instru
Page 43 and 44: CLH - Clear Half Carry Flag Descrip
Page 45 and 46: CLN - Clear Negative Flag Descripti
Page 47 and 48: CLS - Clear Signed Flag Description
Page 49 and 50: CLV - Clear Overflow Flag Descripti
Page 51 and 52: COM - One’s Complement Descriptio
Page 53 and 54: CPC - Compare with Carry Instructio
Page 55 and 56: CPSE - Compare Skip if Equal Instru
Page 57 and 58: EICALL - Extended Indirect Call to
Page 59 and 60: ELPM - Extended Load Program Memory
Page 61 and 62: ESPM - Extended Store Program Memor
Page 63 and 64: FMUL - Fractional Multiply Unsigned
Page 65 and 66: FMULSU - Fractional Multiply Signed
Page 67 and 68: IJMP - Indirect Jump Instruction Se
Page 69: INC - Increment Instruction Set Des
Page 73 and 74: LD (LDD) - Load Indirect from data
Page 75 and 76: LD (LDD) - Load Indirect From data
Page 77 and 78: LDI - Load Immediate Description: L
Page 79 and 80: LPM - Load Program Memory Instructi
Page 81 and 82: LSR - Logical Shift Right Instructi
Page 83 and 84: MOVW - Copy Register Word Instructi
Page 85 and 86: MULS - Multiply Signed Description:
Page 87 and 88: NEG - Two’s Complement Descriptio
Page 89 and 90: OR - Logical OR Instruction Set Des
Page 91 and 92: OUT - Store Register to I/O Locatio
Page 93 and 94: PUSH - Push Register on Stack Instr
Page 95 and 96: RET - Return from Subroutine Instru
Page 97 and 98: RJMP - Relative Jump Instruction Se
Page 99 and 100: ROR - Rotate Right through Carry In
Page 101 and 102: SBC - Subtract with Carry Instructi
Page 103 and 104: SBI - Set Bit in I/O Register Instr
Page 105 and 106: SBIS - Skip if Bit in I/O Register
Page 107 and 108: SBR - Set Bits in Register Instruct
Page 109 and 110: SBRS - Skip if Bit in Register is S
Page 111 and 112: SEH - Set Half Carry Flag Descripti
Page 113 and 114: SEN - Set Negative Flag Description
Page 115 and 116: SES - Set Signed Flag Description:
Page 117 and 118: SEV - Set Overflow Flag Description
Page 119 and 120: SLEEP Description: This instruction
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ST - Store Indirect From Register t
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ST (STD) - Store Indirect From Regi
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ST (STD) - Store Indirect From Regi
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STS - Store Direct to data space In
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SUBI - Subtract Immediate Instructi
Page 131 and 132:
TST - Test for Zero or Minus Instru
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Atmel Headquarters Atmel Operations
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AVR Instruction Set Nomenclature: Status Register (SREG ...

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