AVR Instruction Set Nomenclature: Status Register (SREG ...

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RETI - Return from Interrupt Description: Returns from interrupt. The return address is loaded from the STACK and the global interrupt flag is set. Note that the status register is not automatically stored when entering an interrupt routine, and it is not restored when returning from an interrupt routine. This must be handled by the application program. The stack pointer uses a pre-increment scheme during RETI. Operation: (i) PC(15:0) ← STACK Devices with 16 bits PC, 128K bytes program memory maximum. (ii) PC(21:0) ← STACK Devices with 22 bits PC, 8M bytes program memory maximum. Syntax: Operands: Program Counter: Stack (i) RETI None See Operation SP ← SP + 2 (2 bytes, 16 bits) (ii) RETI None See Operation SP ← SP + 3 (3 bytes, 22 bits) 96 16-bit Opcode: 1001 0101 0001 1000 Status Register (SREG) and Boolean Formula: I T H S V N Z C 1 - - - - - - - I: 1 The I flag is set. Example: extint: ... push ... r0 ; Save r0 on the stack pop r0 ; Restore r0 reti ; Return and enable interrupts Words: 1 (2 bytes) Cycles: 4 devices with 16-bit PC 5 devices with 22-bit PC Instruction Set
RJMP - Relative Jump Instruction Set Description: Relative jump to an address within PC - 2K +1 and PC + 2K (words). In the assembler, labels are used instead of relative operands. For AVR microcontrollers with program memory not exceeding 4K words (8K bytes) this instruction can address the entire memory from every address location. Operation: (i) PC ← PC + k + 1 Syntax: Operands: Program Counter: Stack (i) RJMP k -2K ≤ k < 2K PC ← PC + k + 1 Unchanged 16-bit Opcode: Status Register (SREG) and Boolean Formula: Example: 1100 kkkk kkkk kkkk I T H S V N Z C - - - - - - - - cpi r16,$42 ; Compare r16 to $42 brne error ; Branch if r16 $42 rjmp ok ; Unconditional branch error: add r16,r17 ; Add r17 to r16 inc r16 ; Increment r16 ok: nop ; Destination for rjmp (do nothing) Words: 1 (2 bytes) Cycles: 2 97
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Instruction Set Nomenclature: Statu
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Conditional Branch Summary Instruct
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Instruction Set Summary (Continued)
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Instruction Set Summary (Continued)
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ADC - Add with Carry Description: A
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ADIW - Add Immediate to Word Instru
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ANDI - Logical AND with Immediate I
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BCLR - Bit Clear in SREG Descriptio
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BRBC - Branch if Bit in SREG is Cle
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BRCC - Branch if Carry Cleared Inst
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BREQ - Branch if Equal Instruction
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BRHC - Branch if Half Carry Flag is
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BRID - Branch if Global Interrupt i
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BRLO - Branch if Lower (Unsigned) I
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BRMI - Branch if Minus Instruction
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BRPL - Branch if Plus Instruction S
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BRTC - Branch if the T Flag is Clea
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BRVC - Branch if Overflow Cleared I
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BSET - Bit Set in SREG Description:
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CALL - Long Call to a Subroutine In
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CBR - Clear Bits in Register Instru
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CLH - Clear Half Carry Flag Descrip
Page 45 and 46: CLN - Clear Negative Flag Descripti
Page 47 and 48: CLS - Clear Signed Flag Description
Page 49 and 50: CLV - Clear Overflow Flag Descripti
Page 51 and 52: COM - One’s Complement Descriptio
Page 53 and 54: CPC - Compare with Carry Instructio
Page 55 and 56: CPSE - Compare Skip if Equal Instru
Page 57 and 58: EICALL - Extended Indirect Call to
Page 59 and 60: ELPM - Extended Load Program Memory
Page 61 and 62: ESPM - Extended Store Program Memor
Page 63 and 64: FMUL - Fractional Multiply Unsigned
Page 65 and 66: FMULSU - Fractional Multiply Signed
Page 67 and 68: IJMP - Indirect Jump Instruction Se
Page 69 and 70: INC - Increment Instruction Set Des
Page 71 and 72: LD - Load Indirect from data space
Page 73 and 74: LD (LDD) - Load Indirect from data
Page 75 and 76: LD (LDD) - Load Indirect From data
Page 77 and 78: LDI - Load Immediate Description: L
Page 79 and 80: LPM - Load Program Memory Instructi
Page 81 and 82: LSR - Logical Shift Right Instructi
Page 83 and 84: MOVW - Copy Register Word Instructi
Page 85 and 86: MULS - Multiply Signed Description:
Page 87 and 88: NEG - Two’s Complement Descriptio
Page 89 and 90: OR - Logical OR Instruction Set Des
Page 91 and 92: OUT - Store Register to I/O Locatio
Page 93 and 94: PUSH - Push Register on Stack Instr
Page 95: RET - Return from Subroutine Instru
Page 99 and 100: ROR - Rotate Right through Carry In
Page 101 and 102: SBC - Subtract with Carry Instructi
Page 103 and 104: SBI - Set Bit in I/O Register Instr
Page 105 and 106: SBIS - Skip if Bit in I/O Register
Page 107 and 108: SBR - Set Bits in Register Instruct
Page 109 and 110: SBRS - Skip if Bit in Register is S
Page 111 and 112: SEH - Set Half Carry Flag Descripti
Page 113 and 114: SEN - Set Negative Flag Description
Page 115 and 116: SES - Set Signed Flag Description:
Page 117 and 118: SEV - Set Overflow Flag Description
Page 119 and 120: SLEEP Description: This instruction
Page 121 and 122: ST - Store Indirect From Register t
Page 123 and 124: ST (STD) - Store Indirect From Regi
Page 125 and 126: ST (STD) - Store Indirect From Regi
Page 127 and 128: STS - Store Direct to data space In
Page 129 and 130: SUBI - Subtract Immediate Instructi
Page 131 and 132: TST - Test for Zero or Minus Instru
Page 133: Atmel Headquarters Atmel Operations
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AVR Instruction Set Nomenclature: Status Register (SREG ...

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