AVR Instruction Set Nomenclature: Status Register (SREG ...

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Example: ; This example shows ESPM write of one word for devices with page write clr r31 ; Clear Z high byte clr r30 ; Clear Z low byte ldi r16,$F0 ; Load RAMPZ register out RAMPZ, r16 ; ldi r16, $CF ; Load data to store mov r1, r16 ldi r16, $FF mov r0, r16 ldi r16,$03 ; Enable ESPM, erase page out SPMCR, r16 ; espm ; Erase page starting at $F00000 ldi r16,$01 ; Enable ESPM, store R1:R0 to temporary buffer out SPMCR, r16 ; espm ; Execute ESPM, store R1:R0 to temporary buffer location $F00000 ldi r16,$05 ; Enable ESPM, write page out SPMCR, r16 ; espm ; Execute SPM, store temporary buffer to program memory page starting at $F00000 Words: 1 (2 bytes) Cycles: depends on the operation 62 Instruction Set
FMUL - Fractional Multiply Unsigned Description: This instruction performs 8-bit × 8-bit → 16-bit unsigned multiplication and shifts the result one bit left. Rd Rr R1 R0 Multiplicand × Multiplier → Product High Product Low 8 8 16 Instruction Set Let (N.Q) denote a fractional number with N binary digits left of the radix point, and Q binary digits right of the radix point. A multiplication between two numbers in the formats (N1.Q1) and (N2.Q2) results in the format ((N1+N2).(Q1+Q2)). For signal processing applications, the format (1.7) is widely used for the inputs, resulting in a (2.14) format for the product. A left shift is required for the high byte of the product to be in the same format as the inputs. The FMUL instruction incorporates the shift operation in the same number of cycles as MUL. The multiplicand Rd and the multiplier Rr are two registers containing unsigned fractional numbers where the implicit radix point lies between bit 6 and bit 7. The 16-bit unsigned fractional product with the implicit radix point between bit 14 and bit 15 is placed in R1 (high byte) and R0 (low byte). Operation: (i) R1:R0 ← Rd × Rr (unsigned (1.15) ← unsigned (1.7) × unsigned (1.7)) Syntax: Operands: Program Counter: (i) FMUL Rd,Rr 16 ≤ d ≤ 23, 16≤ r ≤ 23 PC ← PC + 1 16-bit Opcode: 0000 0011 0ddd 1rrr Status Register (SREG) and Boolean Formula: I T H S V N Z C - - - - - - ⇔ ⇔ C: R16 Set if bit 15 of the result before left shift is set; cleared otherwise. Z: R15 •R14 •R13 •R12 •R11 •R10 •R9 •R8 •R7• R6• R5• R4• R3• R2 •R1• R0 Set if the result is $0000; cleared otherwise. R (Result) equals R1,R0 after the operation. Example: fmul r23,r22 ; Multiply unsigned r23 and r22 in (1.7) format, result in (1.15) format movw r22,r0 ; Copy result back in r23:r22 Words: 1 (2 bytes) Cycles: 2 63
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Instruction Set Nomenclature: Statu
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Conditional Branch Summary Instruct
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Instruction Set Summary (Continued)
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Instruction Set Summary (Continued)
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ADC - Add with Carry Description: A
Page 11 and 12: ADIW - Add Immediate to Word Instru
Page 13 and 14: ANDI - Logical AND with Immediate I
Page 15 and 16: BCLR - Bit Clear in SREG Descriptio
Page 17 and 18: BRBC - Branch if Bit in SREG is Cle
Page 19 and 20: BRCC - Branch if Carry Cleared Inst
Page 21 and 22: BREQ - Branch if Equal Instruction
Page 23 and 24: BRHC - Branch if Half Carry Flag is
Page 25 and 26: BRID - Branch if Global Interrupt i
Page 27 and 28: BRLO - Branch if Lower (Unsigned) I
Page 29 and 30: BRMI - Branch if Minus Instruction
Page 31 and 32: BRPL - Branch if Plus Instruction S
Page 33 and 34: BRTC - Branch if the T Flag is Clea
Page 35 and 36: BRVC - Branch if Overflow Cleared I
Page 37 and 38: BSET - Bit Set in SREG Description:
Page 39 and 40: CALL - Long Call to a Subroutine In
Page 41 and 42: CBR - Clear Bits in Register Instru
Page 43 and 44: CLH - Clear Half Carry Flag Descrip
Page 45 and 46: CLN - Clear Negative Flag Descripti
Page 47 and 48: CLS - Clear Signed Flag Description
Page 49 and 50: CLV - Clear Overflow Flag Descripti
Page 51 and 52: COM - One’s Complement Descriptio
Page 53 and 54: CPC - Compare with Carry Instructio
Page 55 and 56: CPSE - Compare Skip if Equal Instru
Page 57 and 58: EICALL - Extended Indirect Call to
Page 59 and 60: ELPM - Extended Load Program Memory
Page 61: ESPM - Extended Store Program Memor
Page 65 and 66: FMULSU - Fractional Multiply Signed
Page 67 and 68: IJMP - Indirect Jump Instruction Se
Page 69 and 70: INC - Increment Instruction Set Des
Page 71 and 72: LD - Load Indirect from data space
Page 73 and 74: LD (LDD) - Load Indirect from data
Page 75 and 76: LD (LDD) - Load Indirect From data
Page 77 and 78: LDI - Load Immediate Description: L
Page 79 and 80: LPM - Load Program Memory Instructi
Page 81 and 82: LSR - Logical Shift Right Instructi
Page 83 and 84: MOVW - Copy Register Word Instructi
Page 85 and 86: MULS - Multiply Signed Description:
Page 87 and 88: NEG - Two’s Complement Descriptio
Page 89 and 90: OR - Logical OR Instruction Set Des
Page 91 and 92: OUT - Store Register to I/O Locatio
Page 93 and 94: PUSH - Push Register on Stack Instr
Page 95 and 96: RET - Return from Subroutine Instru
Page 97 and 98: RJMP - Relative Jump Instruction Se
Page 99 and 100: ROR - Rotate Right through Carry In
Page 101 and 102: SBC - Subtract with Carry Instructi
Page 103 and 104: SBI - Set Bit in I/O Register Instr
Page 105 and 106: SBIS - Skip if Bit in I/O Register
Page 107 and 108: SBR - Set Bits in Register Instruct
Page 109 and 110: SBRS - Skip if Bit in Register is S
Page 111 and 112: SEH - Set Half Carry Flag Descripti
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SEN - Set Negative Flag Description
Page 115 and 116:
SES - Set Signed Flag Description:
Page 117 and 118:
SEV - Set Overflow Flag Description
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SLEEP Description: This instruction
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ST - Store Indirect From Register t
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ST (STD) - Store Indirect From Regi
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ST (STD) - Store Indirect From Regi
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STS - Store Direct to data space In
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SUBI - Subtract Immediate Instructi
Page 131 and 132:
TST - Test for Zero or Minus Instru
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Atmel Headquarters Atmel Operations
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AVR Instruction Set Nomenclature: Status Register (SREG ...

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