AVR Instruction Set Nomenclature: Status Register (SREG ...
AVR Instruction Set Nomenclature: Status Register (SREG ...
AVR Instruction Set Nomenclature: Status Register (SREG ...
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BRBC - Branch if Bit in <strong>SREG</strong> is Cleared<br />
<strong>Instruction</strong> <strong>Set</strong><br />
Description:<br />
Conditional relative branch. Tests a single bit in <strong>SREG</strong> and branches relatively to PC if the bit is cleared. This instruction<br />
branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is<br />
represented in two’s complement form.<br />
Operation:<br />
(i) If <strong>SREG</strong>(s) = 0 then PC ← PC + k + 1, else PC ← PC + 1<br />
Syntax: Operands: Program Counter:<br />
(i) BRBC s,k 0 ≤ s ≤ 7, -64 ≤ k ≤ +63 PC ← PC + k + 1<br />
PC ← PC + 1, if condition is false<br />
16-bit Opcode:<br />
<strong>Status</strong> <strong>Register</strong> (<strong>SREG</strong>) and Boolean Formulae:<br />
Example:<br />
1111 01kk kkkk ksss<br />
I T H S V N Z C<br />
- - - - - - - -<br />
cpi r20,5 ; Compare r20 to the value 5<br />
brbc<br />
...<br />
1,noteq ; Branch if zero flag cleared<br />
noteq:nop ; Branch destination (do nothing)<br />
Words: 1 (2 bytes)<br />
Cycles: 1 if condition is false<br />
2 if condition is true<br />
17