Algorithm Design

796
Epilogue: Algorithms That Run Forever
There are many settings in which we could explore this theme, and as our
final topic for the book we consider one of the most compelling: the design of
algorithms for high-speed packet switching on the Internet.
~ The Problem
A packet traveling from a source to a destination on the Internet can be thought
of as traversing a path in a large graph whose nodes are switches and whose
edges are the cables that link switches together. Each packet p has a header
from which a switch can determine, when p arrives on an input lJ_nk, the output
link on which p needs to depart. The goal of a switch is thus to take streams of
packets arriving on its input links and move each packet, as quickly as possible,
to the particular output link on which it needs to depart. How quickly? In highvolume
settings, it is possible for a packet to arrive on each input link once
ever~ few tens of nanoseconds; if they aren’t offloaded to their respective
output links at a comparable rate, then traffic wil! back up and packets wil!
be dropped.
In order to think about the algorithms operating inside a switch, we model ’
the switch itself as follows. It has n input links I1 ..... In and n output links
On. Packets arrive on the input links; a given packet p has an associated
input/output type (I[p], O[p]) indicating that it has arrived at input link I[p]
and needs to depart on output link O[p]. Time moves in discrete steps; in each
step, at most one new packet arrives on each input link, and at most one
packet can depart on each output link.
Consider the example in Figure E.1. In a single time step, the three packets
p, q, and r have arrived at an empty switch on input links I1, 13, and I4,
respectively. Packet p is destined for 01, packet q is destined for 03, and packet
r is also destined for 03. Now there’s no problem sending packet p out on link
O1; but only one packet can depart on link 03, and so the switch has to resolve
the contention between q and r. How can it do this?
The simplest model of switch behavior is known as pure output queueing,
and it’s essentially an idealized picture of how we wished a switch behaved.
In this model, all nodes that arrive in a given time step are placed in an output
buffer associated with their output link, and one of the packets in each output
buffer actually gets to depart. More concretely, here’s the model of a single
time step.
One step trader pure output queueing:
Packets arrive on input links
Each packet p of type (I~], 0~]) is moved to output buffer 0~]
At most one packet departs from each output buffer
Epilogue: Algorithms That Run Forever
_____------ 0 2
Figure E.1 A switch with n = 4 inputS and outputs. In one time step, packets p, q, and r
have arrived.
So, in Figure E. 1, the given time step could end with packets p and q having
departed on their output links, and with packet r sitting in the output buffer
03. (In discussing this example here and below, we’ll assume that q is favored
over r when decisions are made.) Under this model, the switch is basically
a "fricfionless" object through which packets pass unimpeded to their output
buffer.
In reality, however, a packet that arrives on an input link must be copied
over to its appropriate output link, and this operation requires some processing
that ties up both the input and output links for a few nanoseconds. So, rea!ly,
constraints within the switch do pose some obstacles to the movement of
packets from inputs to outputs.
The most restrictive model of these constraints, input/output queueing,
works as follows. We now have an input buffer for each input link I, as
well as an output buffer for each output link O. When each packet arrives, it
immediately lands in its associated input buffer. In a single time step, a switch
can read at most one packet from each input buffer and write at most one
packet to each output buffer. So under input/output queueing, the example of
Figure E.1 would work as follows. Each of p, q, and r would arrive in different
input buffers; the switch could then move p and q to their output buffers, but
it could not move all three, since moving al! three would involve writing two
packets into the output buffer 03. Thus the first step would end with p and
q having departed on their output links, and r sitting in the input buffer 14
(rather than in the output buffer 03).
More generally, the restriction of limited reading and writing amounts to
the following: If packets Pl ..... p~ are moved in a single time step from input
797