Full Custom IC Desig..

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Part 3: Simulation and Analysis Environment (SAE) We need to run two types of simulation on our design: a) DC sweep analysis. (dc) b) Transient Analysis. (tran) To run SAE, go to Tools menu SAE in the schematic window. This will launch the window in Fig. 20, which consists of three main parts. 1. <strong>Desig</strong>n Variables section. 2. Output Section. (Choose the variables to be displayed after simulation). 3. Enabled analysis for this test bench. Figure: 20: SAE Main Window The bar on the right contains the short cuts for the most commonly used commands in SAE. To set up simulation options: San Francisco State University Nano‐electronics and Computing Research Lab 20
1. Choose the appropriate Models for you instances. (transistors) a. Go to Setup Models Files. b. See window in Fig. 21. c. Click in section one. Use the file browser to determine the directory of your models library file. In the example, you will find it under: /packages/process_kit/generic/generic_90nm/updated_oct2010/SAED_PDK90nm /hspice/SAED90nm.lib d. In section two chose your transistor corner type (i.e. TT,FF,SS,SF and FS). Pick TT_12. e. Click OK. Figure 21: Models Files Window 2. To select the analysis type: a. Go to Setup Analysis, the window in Fig.22 will appear. b. Stay in the General tab. c. Select tran. (For transient analysis) i. Fill out the options as shown in Fig.22, where: ii. Start Time = when the simulation begins. iii. Time Step = when to recalculate the variables. iv. Stop Time = when to stop your simulation. d. Now check the enable box at the lower left corner. e. Click Apply. f. Select dc. (For DC sweep) i. Fill out the options as shown in Fig.23, where: ii. Sweep Variable = the variable you want to change. (Select Source) iii. Sweep type= describe the relation between sweep points. iv. Start = min value for the variable. v. Stop = the Max value for the variable. San Francisco State University Nano‐electronics and Computing Research Lab 21
Page 1 and 2: Full Custom IC Design Flow Tutorial
Page 3 and 4: Introduction This manual assumes yo
Page 5 and 6: Figure 1: Shell commands Custom Des
Page 7 and 8: Figure 4: New Cell View After you c
Page 9 and 10: Figure 8: PMOS and NMOS Next add wi
Page 11 and 12: Adding Pins To add pins to the sche
Page 13 and 14: Figure 13: Schematic with Pins San
Page 15 and 16: Figure 15: Inverter Symbol You may
Page 17 and 18: Figure 17: Drawing an Instance of a
Page 19: Figure 19: Edit property You final
Page 23 and 24: Figure 23: DC Simulation Window 3.
Page 25 and 26: Figure 24: Clicking on the Schemati
Page 27 and 28: Figure 26: Save State Window To run
Page 29 and 30: Figure 28: Transient Analysis Wave
Page 31 and 32: Figure 31: Grouping Waveforms Delay
Page 33 and 34: Figure 33: Delay Waveform Measureme
Page 35 and 36: Figure 35: Rise/Fall Waveform Measu
Page 37 and 38: Figure 37: Average Waveform Measure
Page 39 and 40: Figure 39: Frequency Waveform Measu
Page 41 and 42: Figure 41: Layout Window Go to rule
Page 43 and 44: Figure 44: Layout with NWell and Di
Page 45 and 46: Figure 46: Drawing a Path San Franc
Page 47 and 48: Figure 48: Drawing Contacts Select
Page 49 and 50: Figure 51: Labeling Connections San
Page 51 and 52: Figure 53: DRC Setup Click OK. Afte
Page 53 and 54: Figure 57: DRC Errors San Francisco
Page 55 and 56: In the layout window go to Verifica
Page 57 and 58: Under Control Variables tab set DEC
Page 59 and 60: Figure 63: LVS Done Confirmation Al
Page 61 and 62: Figure 66: LPE Setup Main Tab Under
Page 63 and 64: Under Output Options tab type make
Page 65 and 66: Figure 70: Passing LPE After LPE ha
Page 67 and 68: Figure 72: Parasitic View Zoom You
Page 69 and 70: Figure 74: Testbench Circuit for In
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Figure 76: Hierarchy Editor In orde
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Figure 78: Open Design with Parasit
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Now go ahead and simulate your circ
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For the pins, go to Add Pins and p
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Figure 84: Ring Oscillator Symbol N
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window. In the add instance window,
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instances of the inverter layout on
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Figure 90: Ring Oscillator Layout F
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Debug any DRC errors that come up.
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At this point if there are any LVS
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If LPE ran successfully, a parasiti
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Figure 99: Configurations File Setu
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Figure 101: Ring Oscillator Testben
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Figure 103: Setting up Convergence
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