Full Custom IC Desig..

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Under Netlisting Option tab, for the netlister, select: CDL if not already selected. See Fig. 60. Figure 60: LVS Setup Netlisting Options Tab San Francisco State University Nano‐electronics and Computing Research Lab 56
Under Control Variables tab set DEC_TYPE Value to PEX_DECK, see fig. 61. Figure 61: LVS Setup Control Variables Tab San Francisco State University Nano‐electronics and Computing Research Lab 57
Page 1 and 2:
Full Custom IC Design Flow Tutorial
Page 3 and 4:
Introduction This manual assumes yo
Page 5 and 6: Figure 1: Shell commands Custom Des
Page 7 and 8: Figure 4: New Cell View After you c
Page 9 and 10: Figure 8: PMOS and NMOS Next add wi
Page 11 and 12: Adding Pins To add pins to the sche
Page 13 and 14: Figure 13: Schematic with Pins San
Page 15 and 16: Figure 15: Inverter Symbol You may
Page 17 and 18: Figure 17: Drawing an Instance of a
Page 19 and 20: Figure 19: Edit property You final
Page 21 and 22: 1. Choose the appropriate Models fo
Page 23 and 24: Figure 23: DC Simulation Window 3.
Page 25 and 26: Figure 24: Clicking on the Schemati
Page 27 and 28: Figure 26: Save State Window To run
Page 29 and 30: Figure 28: Transient Analysis Wave
Page 31 and 32: Figure 31: Grouping Waveforms Delay
Page 33 and 34: Figure 33: Delay Waveform Measureme
Page 35 and 36: Figure 35: Rise/Fall Waveform Measu
Page 37 and 38: Figure 37: Average Waveform Measure
Page 39 and 40: Figure 39: Frequency Waveform Measu
Page 41 and 42: Figure 41: Layout Window Go to rule
Page 43 and 44: Figure 44: Layout with NWell and Di
Page 45 and 46: Figure 46: Drawing a Path San Franc
Page 47 and 48: Figure 48: Drawing Contacts Select
Page 49 and 50: Figure 51: Labeling Connections San
Page 51 and 52: Figure 53: DRC Setup Click OK. Afte
Page 53 and 54: Figure 57: DRC Errors San Francisco
Page 55: In the layout window go to Verifica
Page 59 and 60: Figure 63: LVS Done Confirmation Al
Page 61 and 62: Figure 66: LPE Setup Main Tab Under
Page 63 and 64: Under Output Options tab type make
Page 65 and 66: Figure 70: Passing LPE After LPE ha
Page 67 and 68: Figure 72: Parasitic View Zoom You
Page 69 and 70: Figure 74: Testbench Circuit for In
Page 71 and 72: Figure 76: Hierarchy Editor In orde
Page 73 and 74: Figure 78: Open Design with Parasit
Page 75 and 76: Now go ahead and simulate your circ
Page 77 and 78: For the pins, go to Add Pins and p
Page 79 and 80: Figure 84: Ring Oscillator Symbol N
Page 81 and 82: window. In the add instance window,
Page 83 and 84: instances of the inverter layout on
Page 85 and 86: Figure 90: Ring Oscillator Layout F
Page 87 and 88: Debug any DRC errors that come up.
Page 89 and 90: At this point if there are any LVS
Page 91 and 92: If LPE ran successfully, a parasiti
Page 93 and 94: Figure 99: Configurations File Setu
Page 95 and 96: Figure 101: Ring Oscillator Testben
Page 97 and 98: Figure 103: Setting up Convergence
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