Full Custom IC Desig..

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packages/process_kit/generic/generic_90nm/updated_oct2010/SAED_PDK90nm/techfiles/saed 90nm_1p9m_cd.tf After you have filled out the name, directory, and import file, click OK. See Fig.3. Figure 3: New Library Part 2: Creating a Cell View Use File New CellView to create a new Cell View under the library that you create in part 1 (In this case called mylibrary). Enter a name for “Cell Name” and choose schematic for “View Name”. For the “Editor” choose SE-schematic (see Fig.4). Click OK. San Francisco State University Nano‐electronics and Computing Research Lab 6
Figure 4: New Cell View After you click Ok new window will open up called schematic editor (Fig.5) Figure 5: Schematic Editor Window In here we need to make sure that we are in right library. From your console window select Tools Technology Manager and then make sure the attachment of your library (in this case “mylibrary”) is SAED_PDK_90. If not, please click on it and change it (Fig.6). Figure 6: Technology Manager San Francisco State University Nano‐electronics and Computing Research Lab 7
Page 1 and 2: Full Custom IC Design Flow Tutorial
Page 3 and 4: Introduction This manual assumes yo
Page 5: Figure 1: Shell commands Custom Des
Page 9 and 10: Figure 8: PMOS and NMOS Next add wi
Page 11 and 12: Adding Pins To add pins to the sche
Page 13 and 14: Figure 13: Schematic with Pins San
Page 15 and 16: Figure 15: Inverter Symbol You may
Page 17 and 18: Figure 17: Drawing an Instance of a
Page 19 and 20: Figure 19: Edit property You final
Page 21 and 22: 1. Choose the appropriate Models fo
Page 23 and 24: Figure 23: DC Simulation Window 3.
Page 25 and 26: Figure 24: Clicking on the Schemati
Page 27 and 28: Figure 26: Save State Window To run
Page 29 and 30: Figure 28: Transient Analysis Wave
Page 31 and 32: Figure 31: Grouping Waveforms Delay
Page 33 and 34: Figure 33: Delay Waveform Measureme
Page 35 and 36: Figure 35: Rise/Fall Waveform Measu
Page 37 and 38: Figure 37: Average Waveform Measure
Page 39 and 40: Figure 39: Frequency Waveform Measu
Page 41 and 42: Figure 41: Layout Window Go to rule
Page 43 and 44: Figure 44: Layout with NWell and Di
Page 45 and 46: Figure 46: Drawing a Path San Franc
Page 47 and 48: Figure 48: Drawing Contacts Select
Page 49 and 50: Figure 51: Labeling Connections San
Page 51 and 52: Figure 53: DRC Setup Click OK. Afte
Page 53 and 54: Figure 57: DRC Errors San Francisco
Page 55 and 56: In the layout window go to Verifica
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Under Control Variables tab set DEC
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Figure 63: LVS Done Confirmation Al
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Figure 66: LPE Setup Main Tab Under
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Under Output Options tab type make
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Figure 70: Passing LPE After LPE ha
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Figure 72: Parasitic View Zoom You
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Figure 74: Testbench Circuit for In
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Figure 76: Hierarchy Editor In orde
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Figure 78: Open Design with Parasit
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Now go ahead and simulate your circ
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For the pins, go to Add Pins and p
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Figure 84: Ring Oscillator Symbol N
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window. In the add instance window,
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instances of the inverter layout on
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Figure 90: Ring Oscillator Layout F
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Debug any DRC errors that come up.
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At this point if there are any LVS
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If LPE ran successfully, a parasiti
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Figure 99: Configurations File Setu
Page 95 and 96:
Figure 101: Ring Oscillator Testben
Page 97 and 98:
Figure 103: Setting up Convergence
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