Full Custom IC Desig..

Running LVS
The LVS (Layout versus Schematic) check performs LVS comparison to verify that the design
layout accurately represents the electronic equivalent of the design schematic. Hercules LVS
verifies whether the physical design design matches the schematic by: extracting the devices,
verifying the connectivity between the devices and comparing the extracted information with the
schematic netlist.
Notice that in order to pass LVS, schematic names and layout names must match one to one.
Also transistor dimensions for gate width and length in layout and schematic must match.
See figure 58 for reference.
Figure 58: Layout versus Schematic
San Francisco State University Nano‐electronics and Computing Research Lab 54