Full Custom IC Desig..

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Figure 100: Configurations File Setup Afterwards a schematic window opens up with the ring oscillator testbench circuit created earlier, see figure 101 for reference. To check if the parasitics were properly loaded into the ring oscillator, double click the ring oscillator symbol and the parasitics view generated from LPE earlier should display. San Francisco State University Nano‐electronics and Computing Research Lab 94
Figure 101: Ring Oscillator Testbench Circuit From the ring oscillator testbench window, you can simulate the circuit by using SAE as noted in part 3 of the tutorial. To open SAE, go to Tools SAE from the schematics window and setup the simulation for a transient analysis and plot the voltages for the VIO1, VIO2, VIO3, VIO4, and VIO5 voltages. Side Notes for Using Convergence Aids to Initialize Voltages: Also note that it may be helpful to give a wire in the circuit an initial voltage before running simulation. This particular setup applies to circuits such as a five stage ring oscillator circuit shown in figure 102. In addition to the setup noted in part 3 for SAE, before running the simulation, go to Setup Convergence Aids in the SAE window. San Francisco State University Nano‐electronics and Computing Research Lab 95
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Full Custom IC Design Flow Tutorial
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Introduction This manual assumes yo
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Figure 1: Shell commands Custom Des
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Figure 4: New Cell View After you c
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Figure 8: PMOS and NMOS Next add wi
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Adding Pins To add pins to the sche
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Figure 13: Schematic with Pins San
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Figure 15: Inverter Symbol You may
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Figure 17: Drawing an Instance of a
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Figure 19: Edit property You final
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1. Choose the appropriate Models fo
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Figure 23: DC Simulation Window 3.
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Figure 24: Clicking on the Schemati
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Figure 26: Save State Window To run
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Figure 28: Transient Analysis Wave
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Figure 31: Grouping Waveforms Delay
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Figure 33: Delay Waveform Measureme
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Figure 35: Rise/Fall Waveform Measu
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Figure 37: Average Waveform Measure
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Figure 39: Frequency Waveform Measu
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Figure 41: Layout Window Go to rule
Page 43 and 44: Figure 44: Layout with NWell and Di
Page 45 and 46: Figure 46: Drawing a Path San Franc
Page 47 and 48: Figure 48: Drawing Contacts Select
Page 49 and 50: Figure 51: Labeling Connections San
Page 51 and 52: Figure 53: DRC Setup Click OK. Afte
Page 53 and 54: Figure 57: DRC Errors San Francisco
Page 55 and 56: In the layout window go to Verifica
Page 57 and 58: Under Control Variables tab set DEC
Page 59 and 60: Figure 63: LVS Done Confirmation Al
Page 61 and 62: Figure 66: LPE Setup Main Tab Under
Page 63 and 64: Under Output Options tab type make
Page 65 and 66: Figure 70: Passing LPE After LPE ha
Page 67 and 68: Figure 72: Parasitic View Zoom You
Page 69 and 70: Figure 74: Testbench Circuit for In
Page 71 and 72: Figure 76: Hierarchy Editor In orde
Page 73 and 74: Figure 78: Open Design with Parasit
Page 75 and 76: Now go ahead and simulate your circ
Page 77 and 78: For the pins, go to Add Pins and p
Page 79 and 80: Figure 84: Ring Oscillator Symbol N
Page 81 and 82: window. In the add instance window,
Page 83 and 84: instances of the inverter layout on
Page 85 and 86: Figure 90: Ring Oscillator Layout F
Page 87 and 88: Debug any DRC errors that come up.
Page 89 and 90: At this point if there are any LVS
Page 91 and 92: If LPE ran successfully, a parasiti
Page 93: Figure 99: Configurations File Setu
Page 97 and 98: Figure 103: Setting up Convergence
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