Full Custom IC Desig..

More documents

Recommendations

Info

Part 5: Creating Layout To draw a layout, it is strongly recommended that you make yourself familiar with the Lambda Rules. This will help in reducing the layout design cycle time and debugging the errors identified by the Design Rules Check (DRC). You can find the guide with the rules for the 90nm technology we are using here: /packages/process_kit/generic/generic_90nm/updated_oct2010/SAED_PDK90nm/documentatio n File: DesignRules.pdf It is also suggested that you run the DRC throughout the layout process, instead of waiting until you have completed your layout to run it. This may help in finding errors you are making early on, and correct your mistake before you repeat throughout the layout. Important: If you have errors in your DRC report, look for the coordinates that are listed by each error. These will allow you to pinpoint where the error is on your layout. First, open Custom DesignerLE. If your project library is already open in Custom DesignerSE, go to File New CellView on you Custom Designer Console. Make sure the name of the cell is the same as the schematic cell you are making the layout for. In this case, it is inverter (see Fig.40). Click OK and the new layout will open (see Fig.41). Figure 40: Creating a New Layout San Francisco State University Nano‐electronics and Computing Research Lab 40
Figure 41: Layout Window Go to ruler by clicking on . Click once to start drawing the ruler and again to end it. Draw two rulers about the lengths shown in figure 42 (about 3 micrometers by 3 micrometers is a good start). Select the NWELL layer in the layers panel on the right and select Create Rectangle (Fig.42). Draw a rectangle that approximately fits the dimensions of the rulers you set. You can always adjust the dimensions of this rectangle by using the tools (stretch) that existed on left side of layout window then clicking the side you want to stretch. San Francisco State University Nano‐electronics and Computing Research Lab 41
Page 1 and 2: Full Custom IC Design Flow Tutorial
Page 3 and 4: Introduction This manual assumes yo
Page 5 and 6: Figure 1: Shell commands Custom Des
Page 7 and 8: Figure 4: New Cell View After you c
Page 9 and 10: Figure 8: PMOS and NMOS Next add wi
Page 11 and 12: Adding Pins To add pins to the sche
Page 13 and 14: Figure 13: Schematic with Pins San
Page 15 and 16: Figure 15: Inverter Symbol You may
Page 17 and 18: Figure 17: Drawing an Instance of a
Page 19 and 20: Figure 19: Edit property You final
Page 21 and 22: 1. Choose the appropriate Models fo
Page 23 and 24: Figure 23: DC Simulation Window 3.
Page 25 and 26: Figure 24: Clicking on the Schemati
Page 27 and 28: Figure 26: Save State Window To run
Page 29 and 30: Figure 28: Transient Analysis Wave
Page 31 and 32: Figure 31: Grouping Waveforms Delay
Page 33 and 34: Figure 33: Delay Waveform Measureme
Page 35 and 36: Figure 35: Rise/Fall Waveform Measu
Page 37 and 38: Figure 37: Average Waveform Measure
Page 39: Figure 39: Frequency Waveform Measu
Page 43 and 44: Figure 44: Layout with NWell and Di
Page 45 and 46: Figure 46: Drawing a Path San Franc
Page 47 and 48: Figure 48: Drawing Contacts Select
Page 49 and 50: Figure 51: Labeling Connections San
Page 51 and 52: Figure 53: DRC Setup Click OK. Afte
Page 53 and 54: Figure 57: DRC Errors San Francisco
Page 55 and 56: In the layout window go to Verifica
Page 57 and 58: Under Control Variables tab set DEC
Page 59 and 60: Figure 63: LVS Done Confirmation Al
Page 61 and 62: Figure 66: LPE Setup Main Tab Under
Page 63 and 64: Under Output Options tab type make
Page 65 and 66: Figure 70: Passing LPE After LPE ha
Page 67 and 68: Figure 72: Parasitic View Zoom You
Page 69 and 70: Figure 74: Testbench Circuit for In
Page 71 and 72: Figure 76: Hierarchy Editor In orde
Page 73 and 74: Figure 78: Open Design with Parasit
Page 75 and 76: Now go ahead and simulate your circ
Page 77 and 78: For the pins, go to Add Pins and p
Page 79 and 80: Figure 84: Ring Oscillator Symbol N
Page 81 and 82: window. In the add instance window,
Page 83 and 84: instances of the inverter layout on
Page 85 and 86: Figure 90: Ring Oscillator Layout F
Page 87 and 88: Debug any DRC errors that come up.
Page 89 and 90: At this point if there are any LVS
Page 91 and 92:
If LPE ran successfully, a parasiti
Page 93 and 94:
Figure 99: Configurations File Setu
Page 95 and 96:
Figure 101: Ring Oscillator Testben
Page 97 and 98:
Figure 103: Setting up Convergence
show all

Full Custom IC Desig..

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?