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The localization method length of 2k. In fact, it is the number of internal states that can be adopted by the register. In turn, the fourth column of Tabl. 3 As it was mentioned, short-type faults are limited exclusively to AND-type shorts between adjacent lines. Each signature that can be read from a specific R-LFSR register unambiguously indicates a specific set of faults in interconnections that make up feedback lines for that register. In other words, the signature brings the information related to the I j line with specification of the fault type that could have occurred at that line or with the meaning that the line is fault free. When the signatures collected in the register R‐LFSR#(i+1) during the 1st and 2nd phases (or in the R‐LFSR#i register during the 3rd and 4th phases) enable identification of the same fault type at the I j line, it is the information that unambiguously determines the fault type that had happened to that line. 1. If the signature lists average number α of mutually different internal states of the 2k-bit R-LFSR register that can be assigned to every fault considered in this study and that may occur at feedback lines of the register. As one can easily see, the average value of α rapidly grows in pace with increase of the k parameter. Thus, it is associated with increase of the probability that all the faults that are allowed for consideration can be detected and mutually differentiated. The columns 5 and 6 of Tabl. 3 make it possible to compare size of the diagnostic dictionary that is necessary respectively for the methods [2, 3] and [5], provided that maximum threefold faults were allowed for a k‐bit fragment of the n‐bit bus, where n ∈ {64, 128}. Moreover, in the case of solution presented in [5] it was assumed that any AND-type short between lines belonging to the neighboring obtained during modules affected only two such modules. Tabl. 2. Signatures obtained in each module for fault f 1 the phase 1 (3) indicates the stuck-at Conclusion Tab. 2. Sygnatury otrzymane w każdym z modułów dla uszkodzenia f 1 zero fault at the line Phase Signatures Fault f 1 I j while the signature for the phase 2 (4) confirms absence of Module (i+1) Module i faults, it means that 1 S the line in question is m F 1; {f 11a, f 11b } 00..000 involved in the ANDtype short with a line 2 S m F 2 ; {f 12 } 11..111 3 00..000 S m F 3 ; {f 13 } or lines that belong to the neighbouring R-LFSR register. 2. If the signature obtained during the phase 2 (4) indicates that a specific set L of mutually adjacent lines of the bus makes up the AND-type short while the signature for the phase 1 (3) confirms that each line of that set is stuck-at zero, it means that lines of the L set are involved in the AND-type short with a line or lines that belong to the neighbouring register. The similar analysis of faults in neighbouring modules as well as familiarity with layout of mutually adjacent modules allows diagnostics of faults (determination how many lines are involved in a short between the modules under test). Size of the diagnostic dictionary Size of the dictionary for various values of the k parameter is quoted in the second column of Tabl. 3. Furthermore, the third column of that table contains number of all mutually different signatures that can be collected for an R-LFSR register with its Tabl. 3. Size of the diagnostic dictionary Tab. 3. Rozmiar sygnaturowego słownika diagnostycznego k 2 3 4 5 6 The proposed method enables detection, localization and identification of faults in interconnections that are organized in a bus structure. The advantage of the method consists in the fact that it guarantees substantial size reduction of the diagnostic dictionary, both in comparison with the dictionary that is used in studies [2, 3] as well as with the solution that is explained in [5]. The proposed method allows reliable and dependable diagnostics of the considered faults that may be experienced for buses with their width as large as few hundreds bits when a diagnostic dictionary is used with the capacity of only about 543 thousand of 32-bit signatures. On the other hand, the drawback of the method is the test duration that is four times longer than is needed for conventional methods. The length m of a test sequence that guarantees high efficiency of the method per a single phase is only 4k > m > 2k [2, 3], so the number of test cycles only insignificantly affects the total duration of the test procedure. The most important factor that determines duration of the test is the time of seeding and time necessary to deliver the collected signatures to the ATE. However, taking account for the number of interconnections that exist in the circuits of SoC type, that time is acceptable from the point of engineering practice. References |DD| #sig α = #sig /|DD| |DD| [2, 3] |DD| [5] n = 64 n = 128 4 241 256 1,06 7,04·10 37 4,96·10 75 3912 8 4226 65536 15,50 6,11·10 28 3,73·10 57 387765 12 19416 16777216 864,09 4,02·10 25 8,71·10 46 4813945 16 53806 4294967296 79823,20 7,03·10 18 4,94·10 37 31383941 20 115396 1,09951E+12 9528160,66 1,57·10 20 2,21·10 35 137706585 24 212186 2,81475E+14 1326548296 8,86·10 15 7,85·10 31 461361525 28 352176 7,20576E+16 2,04607E+11 4,09·10 16 4,86·10 27 1276096345 32 543366 1,84467E+19 3,3949E+13 2,84·10 11 8,08·10 22 3063752325 [1] Koeter J., Sparks S.: Interconnect Testing Using BIST Embedded in IEEE 1149.1 Designs. Proc. of Int. ASIC Conf., 1991, pp. P11-2.1- P11-2.4. [2] Hławiczka A. et al.: Interconnect Faults Identification and localization Using Modified Ring LFSR. Proc. of 11 th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems – DDECS, 2008, pp. 247–250. [3] Hławiczka A. et al.: Application of Modified Ring-LFSR for Interconnect Faults Detection. Proc. of the 15th IEEE Int. Conference Mixed Design of Integrated Circuits and Systems – MIXDES, 2008, pp. 487–492. [4] Jutman A.: At-Speed On-Chip Diagnosis of Board- Level Interconnect Faults. IEEE European Test Symposium – ETS, 2004, pp. 2–9. [5] Garbolino T., Gucwa K., Hławiczka A.: How to Reduce Size of a Signature-based Diagnostic Dictionary Used for Testing of Connections. Proc. of the 13 th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems – DDECS, 2010, pp. 201–204. [6] Attarha A., Nourani M.: Testing interconnects for noise and skew in gigahertz SoC. Proc. of Int. Test Conf., 2001, pp. 305–314. [7] Su C., Tseng W.: Configuration free SoC interconnect BIST methodology. Proc. of Int. Test Conf., 2001, pp. 1033–1038. [8] Pendurkar R., Chatterjee A., Zorian Y.: Switching activity generation with automated BIST synthesis for performance testing of interconnects. IEEE Trans. on CAD/ICS, vol.20, No 9, 2001, pp. 1143–1158. 18 Elektronika 11/2010
The Time-over-Threshold based silicon strip detector readout (Odczyt do krzemowych detektorów paskowych oparty o metodę Time-over-Threshold) mgr KRZYSZTOF KASIŃSKI AGH-University of Science and Technology, Department of Measurement and Instrumentation, Kraków Silicon strip or pixel detector is built of an array of reverse-biased diodes on the common silicon bulk. Doped areas create strips (in strip detectors) or pixels (in pixel detectors) which are sensing areas. The geometry of the detector determines its ability to detect the interaction location in one or two dimensions. The strip detector for example allows for acquisition of single dimension picture with the resolution defined by the strip pitch (typical 25…100 µm) [1]. Certain number of electron-hole pair (related to the photon energy) is generated in the depleted region as the result of photon interaction with the detector. For example, each of the 17.4 keV X-ray photon (Molybdenum) would generate 4833 electron-hole pairs. In the High Energy Physics applications, the particles do not stop in the detector. As they are crossing the detector they leave some part of their energy. For example a minimal ionizing particle (MIP) generates 77 e-h pairs for each 1 µm of its path in the detector (which gives 23000 e-h pairs for the 300 µm thick silicon detector). The generated charge is then acquired at the detector strips creating a nanosecond range current pulse which is then measured at the detector readout electronics [2]. The very small strip (pixel) pitch and their quantity puts significant limitations on the area and the power of each channel of the readout circuitry and forces to develop multichannel integrated circuits in deep submicron technologies. The current pulse from the detector is integrated in the charge sensitive amplifier (CSA) which is the first stage of the readout circuit. As a result, the voltage step occurs at its output with the amplitude equal to the input charge (Q in ) and feedback capacitance (C fb ) ratio. The polarity of this step is related to the input charge polarity. In order to prevent the pulse pile-up at the CSA output the circuits removing the charge acquired in the feedback before the next pulse arrives are necessary (reset circuits). It can be a resistor connected parallel to the feedback capacitor discharging the output voltage step in the time related to the R fb C fb – dependent time constant (Fig. 1). There are three main architectures in the field of the amplitude spectrometry circuits: – Binary readout, – Regular ADC in each or one per several channels, – Wilkinson type ADC in each channel. The binary readout allows only detecting the fact of the charge deposition over the certain threshold. The regular ADC (analog to digital converter) would be the best choice but it is always a tradeoff between the current consumption, area required, resolution achieved and the operation speed. Tight requirements often prevent from finding the good choice and sometimes require using one ADC per several channels which significantly affects the time limits of the whole circuit. The Wilkinson-type ADC (also called the Time-over- Threshold (ToT) processing) can be a possible solution. If the input charge information could be derived from the discriminator output pulse it would be possible to obtain a reasonable resolution while keeping the power consumption and the area low. Motivation The purpose of this work was to design a silicon strip detector readout chain optimized for long strips (30 pF detector capacitance). The channel functionality should cover both charge measurement (electrons and holes) and the ability to timestamp each event. The nominal input charge range is 0…16 fC, recovery time for the input charge of 4 fC should be in the order of one microsecond. Each channel should be supplied by an ADC allowing high speed operation. The power budget for the whole channel is 2 mW. The channel width should not exceed 50 µm. Solutions of the ToT for the strip detectors [3–5] usually use a charge amplifier with a resistor-type reset circuit and a shaper (special filter cascade) but their characteristics (pulse width vs. input charge) is not linear. The key to the linear characteristics in the Time-Over-Threshold architecture can be a feedback circuit which discharges the feedback capacitor by a constant current. Such architectures are already used in pixel readout chips but the detector capacitances there are much smaller [6, 7]. Architecture Fig. 1. Principle of the Charge Sensitive Amplifier (CSA) operation Rys. 1. Zasada działania wzmacniacza ładunkowego The channel consists of the CSA supplied with two, switchable constant-current reset circuits (Fig. 2a). The amplifier is followed by the discriminator circuit. The discriminator differential threshold is set by Th1 and Th2 lines while the actual CSA output DC level spread due to the process variation can be compensated by the 6-bit digital to analog converter (DAC) placed in each channel. The circuit provides the positive output pulse which length is related to the input charge. Elektronika 11/2010 19
Page 3 and 4: ok LI nr 11/2010 • MATERIAŁY •
Page 5 and 6: Streszczenia artykułów ● Summar
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Page 19: Tabl. 1. Seed applied and operation
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Urządzenie do generacji silnych i
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Experimental evaluation In order to
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