Elektronika 2010-11.pdf - Instytut Systemów Elektronicznych ...

Fig. 6. Architecture of a VLSI circuit implementing a fuzzy logic controller based on interval typ-2 fuzzy sets
Rys. 6. Architektura układu VLSI realizującego sterownik rozmyty oparty na interwałowych zbiorach rozmytych 2-go rzędu
and compute the component grades for all the elements
in the universe of discourse. Taking the next
rule causes the resulting membership function of
the output fuzzy set to be updated. This kind of
processing allows to save up to 2*i*n i *2 r switches
in the circuit, where i, n and r are the numbers
of inputs, input fuzzy sets and accuracy bits, respectively.
The algorithms of type reduction and defuzzification,
mentioned in the previous section, were
implemented as a one module since they are essentially
based on the same set of operations and
therefore share the same building blocks: adders,
multiplication and division circuits. The aim of type
reduction is to map the output interval type-2 fuzzy
set, obtained in the inference module, into a classical
interval fuzzy set. The iterative KM algorithm has to be
executed twice per each output to find the left y L
and the right
y R
bounds of the output interval type-1 set. The ΣΠ and Σ blocks
compute iteratively the numerator and denominator of (6),
respectively. After that, the result of division is stored in the
register, selected by the FSM depending on the stage of algorithm.
At the end of each pass of algorithm, one of the output
registers R L
or R R
is loaded with the appropriate value of y L
or
y R
bound, respectively. The crisp output value is finally computed
in the Σ/2 block as their arithmetic mean.
Experimental results
The proposed type-2 FLC circuit was implemented in the
standard cells approach using CMOS 90 nm technology. The
VHDL model is highly parameterized which means, that depending
on purpose, one can specify: the number of input and
output signals, the number of input and output fuzzy sets, the
type of fuzzy sets (singleton, triangle, trapezoid) and finally the
number of accuracy bits.
Tabl. 1. Design parameters of the FLC circuit in CMOS 90 nm technology
Tab. 1. Parametry układu FLC w technologii CMOS 90 nm
No of
inputs
No of
outputs
No of input
fuzzy
sets
Tabl. 2. Comparison of the parameters of the FLC circuits
Tab. 2. Porównanie parametrów układów FLC
Circuit
No of output
fuzzy
sets
No of cells
Accuracy
Core area
[μm 2 ]
Processing speed
[MFLIPS]
pipelined FLC [4] 470 000 3.125
our FLC 20 000 0.280
Power
[mW]
4 2 4 4 4 38586 0.98
2 4 4 4 4 37230 1.04
4 4 4 4 4 47211 1.19
2 2 4 4 4 28631 0.82
2 2 4 8 4 28631 0.83
2 2 4 4 8 319715 10.16
2 2 8 4 8 319888 10.13
Several experiments with various sets of parameters were
performed in order to check their influence on the area and
power consumption of the FLC circuit. The examples were
chosen in part from practical control applications and reflect
their typical complexity. The circuits were synthesized and
then simulated with the timing parameters of standard cells
from the library.
The results of synthesis and simulation let us estimate the
major parameters of the circuits, which are summarized in
Table 1. The biggest influence on circuit size and power has
the number of accuracy bits, as the sizes of all building blocks
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