Elektronika 2010-11.pdf - Instytut Systemów Elektronicznych ...

Fig. 4. CSA characteristics and output pulse shapes
Rys. 4. Charakterystyki i impulsy wyjściowe ze wzmacniacza ładunkowego
B. Discriminator
The task of the discriminator is to produce an output pulse
lasting as long as the CSA output exceeds certain voltage level,
called the threshold. The presented architecture consists
of several blocks (Fig. 5).
The first stage is the unary-gain differential amplifier
(M 1
–M 4
). Its main task is to convert the single-ended CSA
output signal into fully differential one in order to keep the
operation of the next stage (actual discriminator) most effective.
Additionally, this stage implements both differential
threshold setting (pins Th1 and Th2) and the trimming functionality
(DAC pin). The fully differential discriminator with
hysteresis (M 5
– M 10
) has been described in details by P. Allen
[9]. The transistors are sized to reach the high gain. The
complex, cross-coupled load structure (M 7
– M 10
) introduces
the hysteresis which prevents the multiple, short discriminator
pulses resulting from the noise. M 11
– M 14
transistors provide
the full swing output and increase the overall gain of the
discriminator. In order to uniform the output pulse polarity no
matter what is the polarization of the input charge, the pulse
is inverted or buffered depending on the actual polarity line
configuration.
C. TrimDAC
The purpose of the 6-bit, constant-current architecture Trim-
DAC is to compensate for the CSA output DC level deviation
(Fig. 6). Since the threshold is set globally for all the channels,
the deviation changes the effective threshold setting. The reference
currents for the DAC are to be set externally for both
range and offset. The register supports the initialization to the
default value which is equal to the half of the full range. The
common-centroid layout has been used. The presented circuit
keeps the linearity in the operation range and offset values
exceeding the expected ones (resulting from the monte-carlo
analysis).
Fig. 5. Architecture of the discriminator Rys. 5. Architektura dyskryminatora
Fig. 6. Simplified TrimDAC architecture (register, decoder and references are not included)
Rys. 6. Uproszczony schemat układu TrimDAC (rejestr, dekoder oraz obwody referencyjne są pominięte)
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