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citor C R = 5 pF. In addition to complying with LVDS standard a designed LVDS driver had to be able to transmit data at speed 400 Mb/s (more than 1 Gb/s for C R = 1 pF) and dissipate as low power as possible. The designed circuit was implemented in CMOS 180 nm technology with 1.8 V supply voltage. A. LVDS core To minimize dissipated power it is very important to choose appropriate core architecture. Lots of LVDS driver solutions can be found in publications [6–11]. Fig. 4. Common Mode Feedback circuit [6] Rys. 4. Układ sprzężenia zwrotnego CMFB [6] Fig. 3. LVDS core: Bridged-Switched Current Sources architecture [6] Rys. 3. Rdzeń LVDS: architektura mostkowa [6] Bridged-Switched Current Sources (BSCS) architecture, shown in Fig. 3, is a typical solution [6, 8] for LVDS driver. It consist of two current sources M1, M6 and four MOS switches M2-M5 connected in bridge configuration. To simplify the core transistors’ gates M2-M4 and M3-M5 are shorted and controlled by complementary signal V IN+ and V IN- . Applying logic ‘1’ to V IN+ and logic ‘0’ to V INswitches transistors M3-M4 on and M2-M5 off. As a result a positive differential voltage V DIFF is at the input of receiver – logic ‘1’ was transmitted. In the opposite situation a logic ‘0’ is transmitted. Due to finite on-resistance of PMOS switches and level of common mode voltage V CM BSCS architecture has small headroom in the V DD supply voltage direction. That solution is more suitable for V DD voltage which is equal or above 2.5 V. For supply voltage 1.8 V wider PMOS transistors are necessary. Capacitor C P = 50 pF makes the slew rate of V DIFF voltage shorter thanks to accumulated charges. The value of R P = 10 kΩ resistors used in V CM voltage probe circuit should be large compared with R R resistor and yet small enough to be able to implement in integrated circuit. B. Common mode feedback circuit Fig. 4 presents a implementation of common mode feedback circuit. The V CM common mode voltage at the driver’s output is sensed by resistive divider and compared with V REF reference voltage by the differential amplifier M1-M4. When V CM = V REF the currents flows through M1-M3 and M2-M4 branch of amplifier are equal. Current mirrors used in CMFB (V PMOS and V NMOS potentials) circuit set the output LVDS driver’s current at the desired value. In the contrary, the unequal currents flowing across M3 and M4 are mirrored to M1-M6 core’s transistors and forcing the V CM = V REF voltage. In order to minimize power consumption by CMFB a current ratio of used current mirrors (I core : I CMFB ) were set as 40:1. R BIAS resistor sets the currents flowing through LVDS core and CMFB circuit so it should be implemented carefully in IC. It is also recommended to make 24 the connection with node of R BIAS resistor through the pad to be able to control the driver’s current by external resistor. Stability of designed negative feedback is critical. The phase margin Φ m = 95º ensures high level of negative feedback’s stability. This value is achieved by using a compensation circuit which is a serial combination of R C resistor and C C capacitor. The values: R C = 500 Ω and C C = 10 pF were obtained by AC simulation [12]. C. Band-gap reference source Generation of temperature-independent V REF voltage has been achieved by using band-gap reference source [1]. Implementation of band-gap source requires an operational amplifier, with as low input offset voltage as possible. Designed op amp has a two stage architecture with Miller’s capacitance compensation. A no- Fig. 5. Corners simulation: V REF voltage dependence on temperature Rys. 5. Symulacje brzegowe: zależność napięcia V REF od temperatury Tabl. 1. Corner’s analysis settings Tab. 1. Parametry symulacji brzegowych Corner NMOS PMOS V supply [V] Temp. [ºC] TM typ typ 1.8 25 WP fast fast 1.98 0 WS_TMIN slow slow 1.62 0 WS_TMAX slow slow 1.62 85 WO_TMIN fast slow 1.98 0 WO_TMAX fast slow 1.62 85 WZ_TMIN slow fast 1.98 0 WO_TMAX slow fast 1.62 85 Elektronika 11/2010
minal V REF reference voltage of designed circuit equals 1.23 V, temperature coefficient is 0.3 ppm/ºC at T 0 = 27ºC temperature, V REF voltages changes ΔV REF = 2.4 mV over the temperature range from 0ºC to 85ºC for typical conditions (TM plot in Fig. 5). V REF reference voltage sets the V CM common mode voltage at the driver’s output, so for all above cases an achieved V CM voltage is compatible with IEEE specification. Tabl. 1 presents the corners analysis settings, which were used during the simulation. D. Control block Control block circuit has been implemented as a two chains of inverters with complementary outputs, connected with the shorted gates of LVDS core’s switches. In simplify, the control blocks buffers U DATA driver’s input signal to LVDS core’s inputs. To minimize dynamic control block’s current consumption it is recommended to control the core of driver by the signal with rise/fall time around 0.5 ns. It significantly reduces the spikes of current driven from the supply lines during the switching of inverters. Simulation Results Designed LVDS driver characterizes a very low static 7.5 mW and dynamic 8.5 mW power dissipation at data rate 400 Mb/s (TM plot in Fig. 6). The rise/fall time of V DIFF differential voltage is 710/720 ps so the driver is capable of sending data with maximum rate about 500 Mb/s. The limits of fall/rise time are set by the output driver’s current and C R input capacitance at the receiver side (Fig. 7). According to the formula: dV DIFF I (3) D = C R dt achieving faster changes in V DIFF voltage for constant value of I D is dependent on capacitor’s value C R . Fig. 8 presents the V DIFF voltage at data rate 1.8 Gb/s and C R = 1 pF load. To increase the data rate there can be increased output driver’s current by external resistor connected with R BIAS resistor. That resistor can be also used to set value of V DIFF differential voltage when its desired level is changed by the process technology. Compatibility with IEEE specification limits the current flow across R R = 100 Ω termination resistor to maximum value 4 mA. If the output driver’s current exceeds that limit it is recommended to decrease the resistance visible into receiver’s input. Achieved parameters of designed LVDS driver are shown in Tabl. 2. Fig. 6. Corners simulation: V DIFF voltage at data rate 400 Mb/s, C R = 5 pF Rys. 6. Symulacje brzegowe: napięcie V DIFF , transmisja danych 400 Mb/s, C R = 5 pF Fig. 8. V DIFF voltage at data rate 1.8 Gb/s, C R = 1 pF Rys. 8. Napięcie V DIFF , transmisja danych 1,8 Gb/s, C R = 1 pF Tabl. 2. V DIFF voltage at data rate 1.8 Gb/s, C R = 1 pF Tab. 2. Napięcie V DIFF , transmisja danych 1,8 Gb/s, C R = 1 pF Fig. 7. Maximum data rate dependence on input’s receiver capacitance Rys. 7. Maksymalna szybkość transmisji danych w zależności od pojemności obciążenia Parameter V DIFF differential voltage 400 Mb/s (at C R = 5pF) Data rate 360 mV V CM common mode voltage 1.23V static current consumption dynamic current consumption static power dissipation 4.16 mA 4.16 mA/7.5 mW 1.8Gb/s (at C R = 1pF) 4.7 mA 6.45 mA 7.5 mW dynamic power dissipation 8.5 mW 11.6 mW rise/fall time 710/720ps 180/175ps chip area 0.087 mm 2 Elektronika 11/2010 25
Page 3 and 4: ok LI nr 11/2010 • MATERIAŁY •
Page 5 and 6: Streszczenia artykułów ● Summar
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