Elektronika 2010-11.pdf - Instytut Systemów Elektronicznych ...

The design of low power 11.6 mW high speed 1.8 Gb/s
stand-alone LVDS Driver in 0.18 µm CMOS
(Projekt scalonego nadajnika standardu LVDS o niskim poborze mocy 11,6 mW
i 1,8 Gb/s szybkości transmisji danych)
mgr inż. RAFAŁ KŁECZEK, Akademia Górniczo-Hutnicza, Katedra Metrologii, Kraków
According to Moore’s law CMOS technology has been exponentially
developed over the several recent decades. This development
is particularly visible in digital part where reducing
the effective channel’s length is equivalent to increasing the
frequency of circuits. Growth in the performance of microprocessor
motherboards, optical transmission links, chip-to-chip
communications has created a higher and higher speed requirements
on physical layer interfaces. Due to limited performance
of single link high data rates were achieved by parallelism
in the past, that increased the complexity level and cost
of the fabricated circuits. Nowadays data rates at the range
of few hundred MHz up to or above is necessary. Reducing
the power dissipation is very often one of the most critical modern
circuits’ requirements.
LVDS (Low Voltage Differential Signaling) standard offers
high speed data transmission and low power consumption
at the same time. Due to many advantages of differential
operation: robustness of the link to supply lines and common
mode voltage bouncing, reduction of coupling and radiated
electro-magnetic interference (EMI), higher level of electromagnetic
compatibility (EMC) [1–2] in conjunction with low
voltage swing has become a popular choice for fast data onchip
transmission, on board/backplane or cable connections.
The benefits of LVDS make it valuable technology, that fits
into a wide range of applications such as: PC/computing, telecommunication,
automotive, etc. [3].
This paper presents the design of low-power complete
stand-alone LVDS driver in 180-nm CMOS technology.
It offers a dense packing of transistors and implementation
of mixed-mode circuits. It also occupies low area so makes
the driver suitable for using in multichannel ASIC.
LVDS Interface
LVDS standard was specified by IEEE as a norm that based
on the physical layer defined for the scalable coherent interface
(SCI) [4] (separate industry standard was defined by TIA-
EIA [5]). It specifies the dc and ac parameters for driver and
receiver shown in Fig. 1.
The most important of them are: differential voltage
(V DIFF
= V oa
– V ob
) and common mode voltage V CM
= (V oa
+ V ob
)/2.
A differential voltage is centered at a common mode voltage.
Regarding a value of termination resistor R R
and process, voltage,
temperature (PVT) variations the ranges of this voltages
are defined as:
250 mV ≤ |V DIFF
| ≤ 400 mV (1)
1.125 V ≤ V CM
≤ 1.275 V (2)
For simplicity LVDS transmitter can be considered as current
source with switched polarity, whereas the receiver is a comparator
with hysteresis which can detect voltage signal at the
level of tens of mV. The driver’s output current I D
= 3.6 mA
flows through differential pair lines and termination resistor
R R
= 100 Ω (in most cases R R
= 2R L
, R L
is characteristic impedance
of transmission line). The receiver has a high DC input
impedance so the majority of driver’s output current flows
across R R
resistor and generates at the receiver input about
360 mV, which can be detect as “one” logic state. Switching
driver’s current polarity changes flow direction across R R
resistor,
thereby creating a valid “one” or “zero” logic state.
LVDS Transmitter
A stand-alone LVDS driver can be constructed of the following
functional blocks (Fig. 2):
• LVDS core: current source with switched polarity,
• CMFB: common mode feedback circuit stabilizes the
driver’s output common mode voltage V CM
at the desired
value, which equals V REF
. Output’s voltage V CM
is probed
by resistive divider made of R P
resistors.
• Control block: block responsible for controlling the LVDS
core, it buffers the input signal U DATA
.
• Band-gap: generates a V REF
reference voltage, which should
have no temperature dependence.
During the simulation the receiver was modeled as a parallel
combination of termination resistor R R
= 100 Ω and capa-
Fig. 1. Components of LVDS interface [4]
Rys. 1. Elementy składowe interfejsu LVDS [4]
Fig. 2. Block diagram of LVDS driver
Rys. 2. Schemat blokowy nadajnika standardu
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