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XL Fortran Enterprise Edition for AIX : User's Guide - IBM

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-qtune Option<br />

Syntax<br />

-qtune=implementation<br />

Tunes instruction selection, scheduling, and other implementation-dependent<br />

per<strong>for</strong>mance enhancements <strong>for</strong> a specific implementation of a hardware<br />

architecture. The compiler will use a -qtune setting that is compatible with the<br />

target architecture, which is controlled by the -qarch, -q32, and -q64 options.<br />

If you want your program to run on more than one architecture, but to be tuned to<br />

a particular architecture, you can use a combination of the -qarch and -qtune<br />

options. These options are primarily of benefit <strong>for</strong> floating-point intensive<br />

programs.<br />

By arranging (scheduling) the generated machine instructions to take maximum<br />

advantage of hardware features such as cache size and pipelining, -qtune can<br />

improve per<strong>for</strong>mance. It only has an effect when used in combination with options<br />

that enable optimization.<br />

Although changing the -qtune setting may affect the per<strong>for</strong>mance of the resulting<br />

executable, it has no effect on whether the executable can be executed correctly on<br />

a particular hardware plat<strong>for</strong>m.<br />

Arguments<br />

auto<br />

pwr<br />

pwr2<br />

pwr2s<br />

p2sc<br />

Automatically detects the specific processor type of the compiling<br />

machine. It assumes that the execution environment will be the<br />

same as the compilation environment.<br />

The optimizations are tuned <strong>for</strong> the POWER processors.<br />

The optimizations are tuned <strong>for</strong> the POWER2 processors.<br />

pwrx is a synonym <strong>for</strong> pwr2, but pwr2 is preferred.<br />

The optimizations are tuned <strong>for</strong> the desktop implementation of the<br />

POWER2 architecture, which has a narrower processor-to-memory<br />

bus than other POWER2 implementations. Quad-word instructions,<br />

which are slower on these machines than on other POWER2<br />

machines, are deemphasized to reduce bus contention. That is,<br />

there may be fewer of them or none at all.<br />

The optimizations are tuned <strong>for</strong> the POWER2 Super Chip.<br />

601 The optimizations are tuned <strong>for</strong> the PowerPC 601 processor.<br />

603 The optimizations are tuned <strong>for</strong> the PowerPC 603 processor.<br />

604 The optimizations are tuned <strong>for</strong> the PowerPC 604 processor.<br />

rs64a<br />

rs64b<br />

rs64c<br />

pwr3<br />

pwr4<br />

pwr5<br />

ppc970<br />

The optimizations are tuned <strong>for</strong> the RS64I processor.<br />

The optimizations are tuned <strong>for</strong> the RS64II processor.<br />

The optimizations are tuned <strong>for</strong> the RS64III processor.<br />

The optimizations are tuned <strong>for</strong> the POWER3 processors.<br />

The optimizations are tuned <strong>for</strong> the POWER4 processors.<br />

The optimizations are tuned <strong>for</strong> the POWER5 processors.<br />

The optimizations are tuned <strong>for</strong> the PowerPC 970 processors.<br />

<strong>XL</strong> <strong>Fortran</strong> Compiler-Option Reference 251

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