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Fig. 3
Network synchronization in an expanding digital
network
Fig. 4
Interworking between digital and analog exchanges
With mutual single-ended control every
exchange clock is locked to the average
of all incoming clock frequencies. A
common system frequency is thus obtained
by forcing a number of clocks to
be interdependent. This ensures a reliable
synchronization system, which
makes it possible to use clocks having
lower stability than the clocks in a master-slave
network.
Fig. 3 shows how the different synchronization
methods can be used in a growing
digital network. Initially, when two
digital exchanges are connected by a
PCM link, they are most suitably connected
as master and slave, fig. 3a.
When a transit exchange is added it becomes
the master, fig. 3b When the network
has been extended to include several
transit exchanges and a large number
of local exchanges, mutual singleended
control should be introduced between
the transit exchanges for reasons
of reliability, fig. 3c. But, in order fo ensure
the stability of the network and the
accuracy of the steady state frequency,
one of the transit exchanges is left uncontrolled,
as a sink.
Interwork between digital and analog
exchanges
PCM links between analog and digital
exchanges are equipped with PCM terminals
at the analog end. Such a terminal
has a send and a receive side. The
frequency of the bit streams coming into
the receive side is determined by the
digital exchange. The send side contains
a clock which, if not controlled,
has a frequency accuracy of 50 x 10 6
(50ppm). This clock must be controlled
or else the slip rate may be as high as
one slip every two seconds The control
is accomplished by interconnecting the
send and receive sides of the PCM terminal,
looping, fig.4. This means that the
PCM terminals in the analog exchanges
are slaved to the digital exchanges.
Higher order multiplex systems between
digital and analog exchanges
should be looped in the same way as a
first order multiplex.
Network synchronization in
AXE 10
The AXE 10 system is an example of how
plesiochronous, master-slave and mutual
single-ended control can be implemented
in a telephone exchange, fig.5.
Each method uses a time-discrete regulator
realized in software. This facilitates
almost identical implementation of
all three methods. In fact, the hardware
is identical (oscillators, phase measurement,
D/A converters). Only the software
parameters are different. They vary according
to the method actually used.
The realization of the control in software
also makes it easy to change the synchronization
method during operation.
In both master-slave and mutual singleended
control the regulator is proportional
plus integrating (PI). It should be
noted that in a mutual network all regulators
must be identical, i.e. all PI.
For detailed discussion of integrating
regulators for mutual control, see references
5 and 6. Apart from regulator
algorithm, many other functions are included
in the software, for example a
programmed list of standby links to be
connected if the link from the primary
master fails. All links are also monitored
for phase variations and disturbances.
The input to a mutual regulator is the
sum of the phase errors from up to ten
connected exchanges.
In the case of mutual control based on
integrating regulators, the steady-state
system frequency is secured (in spite of
jitter) by having one of the exchanges
unregulated. Such an exchange is
called a sink because its buffers will accommodate
the total phase error of the
network. The plesiochronous international
exchanges will very well serve as
sinks, fig. 3c. An additional advantage of
using a sink is that it gives the network
an absolute frequency reference and
makes mutual single-ended control immune
to delay variations.
Clock types
In AXE 10 three types of clocks are used,
CLM, RCM and CCM.
CLM
The internal clock of every AXE 10 exchange
consists of three clock modules
(CLM), each with a voltage controlled
crystal oscillator at a frequency of
24.576 MHz. The modules are phase-
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