FINFET Isolation Approaches and Ramifications - SOI Industry ...

IBM SRDC 

FINFET Isolation Approaches and 

Ramifications: Bulk vs. SOI 

Terence Hook 

IBM SRDC 

FDSOI Workshop, Hsinchu, Taiwan, April 22, 2013

IBM Semiconductor Research and Development Center 

Background – FDSOI and FinFETs 

• Fully Depleted Transistors: FDSOI and FinFETs 

– Similarities 

Electrostatics 

Access resistance 

Threshold fluctuations 

– Differences 

Physical Orientation 

Density and “fin effect” 

Backgate and body effect 

• FinFETs on SOI and bulk substrates 

– Process Comparison 

– Fin Taper 

– Isolation doping 

Intrawell 

Interwell 

Drain-source current 

– Self-heating and history effect 

– Transistor mismatch 

– Work function and gate reliability 

– Process variations 

• Conclusion 

FDSOI Workshop Hsinchu, Taiwan April 22, 2013


FDSOI and FinFET transistors 

• The key in both device types is very thin silicon. 

– FDSOI is 5-8nm thick 

– FinFET 8-15nm wide 

– The short-channel effect is set by physical geometry, not doping 

• Both are challenged in getting the current out of the thin body and 

into the contact metal. 

• In principle both FinFET and FDSOI bodies can be undoped 

– The threshold voltage is set by the gate work function 

– Doping can be used to adjust threshold voltage but there are adverse 

implications 

– FinFETs built in bulk silicon inherently require some level of doping 

• While electrical characteristics share some similarities, the structures 

and processes are completely different 




“Conventional” 

FDSOI 

FinFET 

Λ 

S 

Gate 

D 

Λ/2 

S 

Gate 

BOX 

Substrate 

D 

S 

Gate 

Gate 

D 

Λ 

Λ = t dep +ε si /ε ox t ox 

L ~ 1/√N 

• Confinement of field 

lines by doping 

Λ = 2(t si +ε si /ε ox t ox ) 

L min ~ 3t si +9t ox 


lines by BOX 

Λ = t si +ε si /ε ox 2t ox 

L min ~ 1.5t si +9t ox 


lines by gates 

2004 IEEE SOI Short Course 

Huang & Nowak 

D. Frank, et al. 





Finfet 

Thin-body devices use epitaxial silicon deposition on the 

source and drain to dope and “fatten” the body for the 

contact 



Matching 

• Matching is affected by 

several components: 

– Physical variations 

such as line-edgeroughness 

– Electrical variations 

such as metal-gate 

work function 

variations 

– Doping variations 

subject to classic 

Poisson statistical 

variations 

• Undoped FinFET and 

FDSOI are comparable 

calculted σΔVt (mV) 

40 

30 

20 

10 

IEDM 2011 

1.3mV-um 

AVT 

0 

0.00 0.01 0.02 0.03 

1/sqrt(LxW) (nm -1 ) 

VLSI 2011 

1.5mV-um 

• Adding doping degrades 

matching 


FinFET 



PDSOI FDSOI FinFET orientation 

Gate 

Drain 

Gate 

Drain 

Drain 

Current flow 

Source 

Current flow 

Source 

Source 

Source 

Fin 

Gate 

Source 

Current 

flow 

PDSOI 


FinFET 

Electron Mobility (cm 2 V -1 s -1 ) 

500 

400 

Universal (100) curve 

300 

200 

100 

0 

0 5 10 15 

N inv (X10 12 cm -2 ) 

NFET 

180 

PFET 

Hole Mobility (cm 2 V -1 s -1 ) 

160 

140 

120 

100 

V. Basker, IBM, VLSI 2011 

Universal (100) curve 

80 

60 

40 

20 

0 

0 2 4 6 8 1 0 1 2 1 4 16 

N inv (X10 12 cm -2 ) 



The 3D Effect in FinFET 


Effective width ~1X (current and capacitance) 

Aerial width ~0.7X 

FinFET 

• FDSOI is conventionally planar 

– The current drive and device 

capacitance and the layout footprint 

correspond directly 

Footprint width 

Electrical width 

• FinFET is 3-D 

– has more current drive (and also 

capacitance) per layout footprint 

Where the 

gate will be 

fin 



Substrate effect 

375 

370 

Vtsat (mV) 

365 

360 

355 

Backgate 

• In FDSOI the threshold voltage may 

be modulated by the potential on the 

backgate 

• A typical number for a 25nm thick 

BOX is ~60-80mV/V. 

350 

-1.5 -1 -0.5 0 0.5 1 

Pwell Bias (V) 

• In FinFET - even in bulk - the 

substrate bias has little to no effect 

on the device 

• The so-called “body effect” is virtually 

absent, only 3mV/V. 



The Main Event – why SOI FinFETs are better 

• Fully Depleted Transistors: FDSOI and FinFETs 

– Similarities 



Threshold fluctuations 

– Differences 

Physical Orientation 

Density and “fin effect” 

Backgate and body effect 

• FinFETs on SOI and bulk substrates 

– Process Comparison 

– Fin Taper 

– Isolation doping 

Intrawell/Interwell 

Drain-source 

– Self-heating and history effect 

– Transistor mismatch 

– Work function and gate reliability 

– Process variations 

• Conclusion 



FinFETs on Bulk and SOI substrates 

Gate 

Epitaxial Source/drain 

Active Fin 

Sub-fin leakage path 

Junction depth 

Junction Isolation 

Thermal conduction path 

Dielectric Isolation 



FinFet Options: Bulk Isolated, Oxide Isolated 

fin 

Gate Stack 

Fin 

CSD 

Oxide 

Oxide 

Silicon Substrate 


• Bulk isolated 

– Process complex more 

expensive 

– Process integration scheme 

has process control 

challenges 

– Bulk starting wafer 

• Oxide isolated 

– Process simpler less expensive 

– Many control issues improved over 

bulk isolated FinFet 

– SOI starting wafer 



Bulk Isolated FinFet Process (1) 

RIE etch to create fin 

and isolation trench 

Channel Stop Doping 

Resist 

• Starting material: Silicon wafer 

• Add channel stop doping 

• Etch silicon to create fin and isolation trench 

– Blind/timed etch (i.e. no etch stop) 

– Depth control has many variables (local 

pattern density, etch chemistry, local surface 

condition, etc.) 

– Trench must be tapered for good fill 


Ø 

Fin 

fin 

Trench Depth 

Isolation Trench 

CSD 




Bulk Isolated FinFet Process (2) 

Dep/etch Oxide 

Planarize Oxide 

fin 

fin 

CSD 

CSD 

Oxide 

Oxide 



Recess Oxide 

Recess Depth 

fin 

CSD 

Oxide 




SOI FinFet Process 

RIE etch to create fin 

Top Silicon 

Oxide 

Resist 

• Starting material: Silicon wafer with buried 

oxide 

• Etch silicon to create fin stopping on oxide 

– Fin height controlled by starting silicon 

thickness 

– Fin etched profile vertical (no fill constraint) 

– No channel stop doping impinging on the device 


Top Si Thickness 

Fin 

Oxide 




Fin Taper: detrimental to device performance 

• Electrostatics and 

current density vary 

through fin height 

• Massive doping 

suppresses some 

contribution of fat-fin 

region but current 

degraded 

• Output conductance 

for SOI with vertical fin 

empirically 

demonstrated to be 

superior to bulk with 

tapered fin 



Bulk Well Isolation Engineering 

• Bulk FinFETs require 

– Junction isolation masks and implants 

– Well contacts 

– Latchup prevention measures 

Second STI 

Heavily doped substrate 

Pfet-Pfet 



Drain-source Current Suppression 

• Heavy doping: 

– BTB current 

– Nonuniformity 

• Deep gate 

– Capacitance 

– Process challenge 

• Shallow junction 

– Strain reduction 

– Process challenge 



Doping and Matching and Vmin 

• Bulk FinFETs must 

have doping in the subfin 

region 

• Body doping degrades 

transistor matching; 

data presented in VLSI 

2012 

• Transistor mismatch is 

fundamentally 

associated with SRAM 

low-voltage capability 



Doping and Vmax 

• Bulk FinFETs must have 

doping in the sub-fin 

region 

• For a given off-current, 

body doping requires a 

work function closer to 

band edge and the 

electric field is larger 

• The electric field is 

fundamentally associated 

with dielectric reliability 

Undoped 

Doped 

Electric potential across the fin from 

one side to the other for two design 

points with the same threshold 

voltage. 

The electric field is larger for the 

doped fin case. 



Bulk and SOI Voltage Range 

• Combining Vmax 

(WF) and Vmin (RDF) 

the operating voltage 

range of bulk FinFETs 

is inherently more 

restricted than SOI 

FinFETs 

• Representative 

calculations as much 

as 200mV difference 

• This trend is also 

exacerbated by 

scaling 



Bulk and SOI Variation 

• Gate recess: SOI FinFET is 

nearly unaffected by gate 

recess variation 

• Fin Height: SOI fin height is 

less variable than bulk. 

• Doping: Bulk FinFET is 

affected by global doping 

variation in addition to RDF 

• Fin width: Bulk FinFET has 

less sensitivity to fin width is 

because of the doping 

• Overall: Variation due to 

these critical fin formation 

features is smaller in SOI 

than bulk 



Strain, SER, Self-heating 

Minimal strain 

reduction for SOI 



Conclusions 

• FinFETs with SOI and bulk isolation architectures have been compared 

• Key differences: 

– Tapered fin profile intrinsic to bulk degrades electrostatics and uniformity 

– Inter and Intrawell junction isolation requires well implants and latchup prevention 

methods 

– Suppression of sub-fin leakage requires doping 

Doping degrades transistor matching and therefore low-voltage operation 

Doping requires work function nearer band-edge, therefore degrades reliability 

Net result is closure of voltage range window 

– Larger fin height variation and influence of sub-fin conduction region result in larger 

Ieff variation in bulk and therefore loss of potential performance 

– 

• SOI-based FinFET obviates many challenges to realization of FinFET potential 

• SOI-based FinFET is extendable 

• IBM technology offering is based on SOI 



Acknowledgements 

• FinFET research and development has been active at various 

IBM sites for many years. 

• Key results from personnel at these IBM locations have been 

incorporated in this presentation: 

– Albany, New York 

– East Fishkill, New York 

– Essex Junction, Vermont 

– Yorktown Heights, New York 

• Special thanks for the contributions of B. Anderson, A. 

Bryant, Y. Deng, A. Dixit, J. Johnson, E. Nowak, A. Scholze, 

T. Standaert, and R. Vega

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