DDR3 RDIMMs Channel - Micron

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4/12/2007 10 ©2007 Micron Technology, Inc. All rights reserved. Data Channel - Loads • The DDR3 data channel is much like the DDR2 channel, although DDR3 data rates are twice as fast � DDR3 data rates range from 800MT/s to 1,333MT/s and with plans to support up to 1.6GT/s • Most systems will support a maximum of two slots per channel up to 1,066MT/s (or 4 data loads) Number of RDIMMS * DQ Loads DDR3-800 Two - (DR) 4 DDR3-1067 Two - (DR) 4 DDR3-1333 Two - (DR) Target (4) * early assumptions
Improvements to the Data Channel • The DDR3 data channel can run faster due to enhancements in the DDR3 component � DDR3 supports dynamic ODT � Dynamic ODT allows the termination value to change without issuing an MRS command, which essentially changes the ODT termination “onthe-fly” � With Dynamic ODT enabled, the DRAM will switch from {normal} ODT to Dynamic ODT (RTT_WR) when beginning a write burst; and will subsequently switch back to ODT (RTT_nom) at the completion of the write burst � DDR2 ODT values reflect only: 50Ω, 75Ω, 150Ω � DDR3 ODT values include: 20Ω, 30Ω, 40Ω, 60Ω, 120Ω 4/12/2007 11 ©2007 Micron Technology, Inc. All rights reserved.
Page 1 and 2: 4/12/2007 DDR3 RDIMMs Channel Basic
Page 3 and 4: 4/12/2007 DDR3 RDIMM Basics and Int
Page 5 and 6: 4/12/2007 5 ©2007 Micron Technolog
Page 7 and 8: Improved Termination for Post-Regis
Page 9: 4/12/2007 9 ©2007 Micron Technolog
Page 13 and 14: 4/12/2007 13 ©2007 Micron Technolo
Page 17 and 18: • Controller Break out Impedance
Page 19 and 20: • Ron Nominal Drive strength in o
Page 21 and 22: • Typical RDIMM spacing (UDIMM) T
Page 25 and 26: • Address data eye diagrams at th
Page 27 and 28: • Typical frequency response for:
Page 29 and 30: 4/12/2007 DDR3 RDIMM Topology, Simu
Page 31 and 32: Pre Register Address Timing Example
Page 33 and 34: Post Register Address Timing Exampl
Page 41 and 42: 4/12/2007 DDR3 RDIMM Topology, Simu
Page 49 and 50: DRAM On-Die-Termination (ODT) sugge
Page 51 and 52: • WRITEs at DDR3-1066 4/12/2007 5

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