DDR3 RDIMMs Channel - Micron

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4/12/2007 46 ©2007 Micron Technology, Inc. All rights reserved. Data Bus • Single slot populated (DR x4) Clock Rate = 533 MHz • READ from Slot 1, Rank 1 (DDR3-1066) • Signal probed at Controller, Controller ODT = 75 ohm
4/12/2007 47 ©2007 Micron Technology, Inc. All rights reserved. Data Bus • Both slots populated (DR x4) Clock Rate = 533 MHz • READ from Slot 1, Rank 1 (DDR3-1066) • Signal probed at Controller, Controller ODT = 75 ohm
Page 1 and 2: 4/12/2007 DDR3 RDIMMs Channel Basic
Page 3 and 4: 4/12/2007 DDR3 RDIMM Basics and Int
Page 5 and 6: 4/12/2007 5 ©2007 Micron Technolog
Page 7 and 8: Improved Termination for Post-Regis
Page 9 and 10: 4/12/2007 9 ©2007 Micron Technolog
Page 11 and 12: Improvements to the Data Channel
Page 13 and 14: 4/12/2007 13 ©2007 Micron Technolo
Page 17 and 18: • Controller Break out Impedance
Page 19 and 20: • Ron Nominal Drive strength in o
Page 21 and 22: • Typical RDIMM spacing (UDIMM) T
Page 25 and 26: • Address data eye diagrams at th
Page 27 and 28: • Typical frequency response for:
Page 29 and 30: 4/12/2007 DDR3 RDIMM Topology, Simu
Page 31 and 32: Pre Register Address Timing Example
Page 33 and 34: Post Register Address Timing Exampl
Page 41 and 42: 4/12/2007 DDR3 RDIMM Topology, Simu
Page 45: 4/12/2007 45 ©2007 Micron Technolo
Page 49 and 50: DRAM On-Die-Termination (ODT) sugge
Page 51 and 52: • WRITEs at DDR3-1066 4/12/2007 5

DDR3 RDIMMs Channel - Micron

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