DDR3 RDIMMs Channel - Micron

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Post Register Address Timing Example (Light Load) • POST-Register Timing Address to Clock U12 � DDR3-1333 (clock rate = 667.67 MHz) � Single R/C A (SRx8) module in system � Measured at first DRAM to the left of the register U1 U11 U2 U10 Reg •Using a moderate driver 20-25 ohms •Fast Corner •Clock shown as single ended •DRAM tIS = 225ps tIH = 225ps U5 4/12/2007 34 U8 ©2007 Micron Technology, Inc. All rights reserved. U6 U7
Post Register Address Timing Example (Light Load) • POST-Register Timing Address to Clock U12 � DDR3-1333 (clock rate = 667.67 MHz) � Single R/C A (SRx8) module in system � Measured at second DRAM to the left of the register U1 U11 U2 U10 Reg •Using a moderate driver 20-25 ohms •Fast Corner •Clock shown as single ended •DRAM tIS = 225ps tIH = 225ps U5 4/12/2007 35 U8 ©2007 Micron Technology, Inc. All rights reserved. U6 U7
Page 1 and 2: 4/12/2007 DDR3 RDIMMs Channel Basic
Page 3 and 4: 4/12/2007 DDR3 RDIMM Basics and Int
Page 5 and 6: 4/12/2007 5 ©2007 Micron Technolog
Page 7 and 8: Improved Termination for Post-Regis
Page 9 and 10: 4/12/2007 9 ©2007 Micron Technolog
Page 11 and 12: Improvements to the Data Channel
Page 13 and 14: 4/12/2007 13 ©2007 Micron Technolo
Page 17 and 18: • Controller Break out Impedance
Page 19 and 20: • Ron Nominal Drive strength in o
Page 21 and 22: • Typical RDIMM spacing (UDIMM) T
Page 25 and 26: • Address data eye diagrams at th
Page 27 and 28: • Typical frequency response for:
Page 29 and 30: 4/12/2007 DDR3 RDIMM Topology, Simu
Page 31 and 32: Pre Register Address Timing Example
Page 33: Post Register Address Timing Exampl
Page 37 and 38: Post Register Address Timing Exampl
Page 39 and 40: Post Register Address Timing Exampl
Page 41 and 42: 4/12/2007 DDR3 RDIMM Topology, Simu
Page 49 and 50: DRAM On-Die-Termination (ODT) sugge
Page 51 and 52: • WRITEs at DDR3-1066 4/12/2007 5

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