DDR3 RDIMMs Channel - Micron

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4/12/2007 60 ©2007 Micron Technology, Inc. All rights reserved. Micron Development Tools • Use passive probe hardware and software from NEXUS (http://www.nexustechnology.com/) • Modules designed to interface to Tektronics Logic Analyzer • All DQ, clock, command, control and address signals probed with no impact on module functionality � Micron Snoop RDIMMs available – 3Q07 • R/C A • R/C C • R/C D
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4/12/2007 DDR3 RDIMMs Channel Basic
Page 3 and 4:
4/12/2007 DDR3 RDIMM Basics and Int
Page 5 and 6:
4/12/2007 5 ©2007 Micron Technolog
Page 7 and 8:
Improved Termination for Post-Regis
Page 9 and 10: 4/12/2007 9 ©2007 Micron Technolog
Page 11 and 12: Improvements to the Data Channel
Page 13 and 14: 4/12/2007 13 ©2007 Micron Technolo
Page 17 and 18: • Controller Break out Impedance
Page 19 and 20: • Ron Nominal Drive strength in o
Page 21 and 22: • Typical RDIMM spacing (UDIMM) T
Page 25 and 26: • Address data eye diagrams at th
Page 27 and 28: • Typical frequency response for:
Page 29 and 30: 4/12/2007 DDR3 RDIMM Topology, Simu
Page 31 and 32: Pre Register Address Timing Example
Page 33 and 34: Post Register Address Timing Exampl
Page 41 and 42: 4/12/2007 DDR3 RDIMM Topology, Simu
Page 49 and 50: DRAM On-Die-Termination (ODT) sugge
Page 51 and 52: • WRITEs at DDR3-1066 4/12/2007 5
Page 59: 4/12/2007 59 ©2007 Micron Technolo
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DDR3 RDIMMs Channel - Micron

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