DDR3 RDIMMs Channel - Micron

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• System Board Lead-in Length (inches) including breakout (UDIMM) System Board Lead-in Length (inches) including breakout DQ/DQS 1.0" to 7.0" CMD/Address 1.0" to 5.0" Control 1.0" to 5.0" Clocks 1.0" to 5.5" � Byte lane lengths do not need to match, but within each byte lane the lengths and propagation delay should match 4/12/2007 18 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved. General System Assumptions
• Ron Nominal Drive strength in ohms (UDIMM) � Actual register values from different vendors may vary 4/12/2007 19 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved. General System Assumptions Ron Nominal Drive strength in Ohms DQ 30-ohms to 40-ohms (1& 2-slots/ch) Control 30-ohms to 40-ohms (1 & 2-slots/ch) C/A 20-ohms to 40-ohms (2-slots/ch) 30-ohms to 40-ohms (1-slot/ch) Clock 30-ohms to 40-ohms (1 & 2-slots/ch) Controller drives a heaver load on UDIMMs RDIMM controller typically only drives 2 loads
Page 1 and 2: 4/12/2007 DDR3 RDIMMs Channel Basic
Page 3 and 4: 4/12/2007 DDR3 RDIMM Basics and Int
Page 5 and 6: 4/12/2007 5 ©2007 Micron Technolog
Page 7 and 8: Improved Termination for Post-Regis
Page 9 and 10: 4/12/2007 9 ©2007 Micron Technolog
Page 11 and 12: Improvements to the Data Channel
Page 13 and 14: 4/12/2007 13 ©2007 Micron Technolo
Page 17: • Controller Break out Impedance
Page 21 and 22: • Typical RDIMM spacing (UDIMM) T
Page 25 and 26: • Address data eye diagrams at th
Page 27 and 28: • Typical frequency response for:
Page 29 and 30: 4/12/2007 DDR3 RDIMM Topology, Simu
Page 31 and 32: Pre Register Address Timing Example
Page 33 and 34: Post Register Address Timing Exampl
Page 41 and 42: 4/12/2007 DDR3 RDIMM Topology, Simu
Page 49 and 50: DRAM On-Die-Termination (ODT) sugge
Page 51 and 52: • WRITEs at DDR3-1066 4/12/2007 5

DDR3 RDIMMs Channel - Micron

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