DDR3 RDIMMs Channel - Micron

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• System Board Lead-in Nominal Impedance (UDIMM) System Board Lead-in Nominal Impedance and Reference DQ 40-ohms to 50-ohms Ground DQS/DQS (SINGLE ENDED) 40-ohms to 50-ohms Ground CMD/Address 40-ohms to 50-ohms Ground Control 40-ohms to 50-ohms Power Clocks (Differential) 40-ohms to 50-ohms Power � For least amount of noise, all lead-In traces should be “strip-line” � Signals should be power or ground plan reference 4/12/2007 16 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved. General System Assumptions
• Controller Break out Impedance and lengths used for initial simulations (UDIMM) 4/12/2007 17 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved. General System Assumptions Controller Break out Impedance DQ 50-ohms to 60-ohms 0.2" to 1.0" DQS/DQS (SINGLE ENDED) 50-ohms to 60-ohms 0.2" to 1.0" CMD/Address 50-ohms to 60-ohms 0.2" to 1.0" Control 50-ohms to 60-ohms 0.2" to 1.0" Clocks 50-ohms to 60-ohms 0.2" to 1.0" Length range for breakout
Page 1 and 2: 4/12/2007 DDR3 RDIMMs Channel Basic
Page 3 and 4: 4/12/2007 DDR3 RDIMM Basics and Int
Page 5 and 6: 4/12/2007 5 ©2007 Micron Technolog
Page 7 and 8: Improved Termination for Post-Regis
Page 9 and 10: 4/12/2007 9 ©2007 Micron Technolog
Page 11 and 12: Improvements to the Data Channel
Page 13 and 14: 4/12/2007 13 ©2007 Micron Technolo
Page 15: 4/12/2007 15 ©2007 Micron Technolo
Page 19 and 20: • Ron Nominal Drive strength in o
Page 21 and 22: • Typical RDIMM spacing (UDIMM) T
Page 25 and 26: • Address data eye diagrams at th
Page 27 and 28: • Typical frequency response for:
Page 29 and 30: 4/12/2007 DDR3 RDIMM Topology, Simu
Page 31 and 32: Pre Register Address Timing Example
Page 33 and 34: Post Register Address Timing Exampl
Page 41 and 42: 4/12/2007 DDR3 RDIMM Topology, Simu
Page 49 and 50: DRAM On-Die-Termination (ODT) sugge
Page 51 and 52: • WRITEs at DDR3-1066 4/12/2007 5

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