DDR3 RDIMMs Channel - Micron

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Post Register Address Timing Example (Light Load) • Topology for address/command/control left side U12 U1 U11 U2 U10 Reg 4/12/2007 32 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved. U5 Register VTT U8 U6 60 ohm Trace All Dimensions are in mm 47 Ω U7 3.1 1.1 18.9 13.6 13.6 13.6 13.6 8.9 3.7 3.7 3.7 3.7 3.7 SDRAM SDRAM SDRAM SDRAM SDRAM
Post Register Address Timing Example (Light Load) • Topology for clock left side REGISTER 60 ohm Trace 0.6 5 All dimensions are in mm 19 4/12/2007 33 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved. 13.6 13.6 2.3 SDRAM 13.6 U12 2.3 SDRAM 2.3 U1 U11 13.6 U2 SDRAM 2.3 U10 Reg SDRAM 10.3 U5 2.3 U8 U6 0.1 uF 47 ohm 1.2 U7 SDRAM VDD
Page 1 and 2: 4/12/2007 DDR3 RDIMMs Channel Basic
Page 3 and 4: 4/12/2007 DDR3 RDIMM Basics and Int
Page 5 and 6: 4/12/2007 5 ©2007 Micron Technolog
Page 7 and 8: Improved Termination for Post-Regis
Page 9 and 10: 4/12/2007 9 ©2007 Micron Technolog
Page 11 and 12: Improvements to the Data Channel
Page 13 and 14: 4/12/2007 13 ©2007 Micron Technolo
Page 17 and 18: • Controller Break out Impedance
Page 19 and 20: • Ron Nominal Drive strength in o
Page 21 and 22: • Typical RDIMM spacing (UDIMM) T
Page 25 and 26: • Address data eye diagrams at th
Page 27 and 28: • Typical frequency response for:
Page 29 and 30: 4/12/2007 DDR3 RDIMM Topology, Simu
Page 31: Pre Register Address Timing Example
Page 35 and 36: Post Register Address Timing Exampl
Page 41 and 42: 4/12/2007 DDR3 RDIMM Topology, Simu
Page 49 and 50: DRAM On-Die-Termination (ODT) sugge
Page 51 and 52: • WRITEs at DDR3-1066 4/12/2007 5

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