FALCOM JP18 GPS receiver - Hardware manual

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JP18 FALCOM GPS RECEIVER VERSION 1.0.7 5 TECHNICAL DESCRIPTION 5.1 Receiver Architecture The JP18 OEM GPS receiver from FALCOM is a new OEM GPS receiver product that features the SiRFstarIII single chipset. The core of JP18 units is comprised of the GSC3LPf that includes the Digital and RF in a single chip. The SiRFstarIII-LT DSP core processes the incoming baseband samples and outputs GPS satellite pseudo-range measurements for storage in on-board SRAM. Once in DSP SRAM, the pseudo-range measurements are then available for further processing by the ARM7TDMI-S to calculate position, speed, heading, and time. The firmware for ARM7TDMI-S is stored and executed directly from either the onboard 4 Mbit ROM or 4 Mbit FLASH memory. The calculated position, speed, heading, and time data is stored in CPU SRAM, which is then formatted in the selected data format (NMEA, SiRF Standard Binary (SSB), or AI3/F) for transfer to the host via the UART. In Assisted-GPS applications, the use of Location Protocol Libraries (provided by SiRF) running on the host, the navigation data can be converted to other industry standard location protocols such as RRLP, RRC, NMEA and PDDM. Figure 2: Receiver architecture of the JP18 GPS receiver. Figure 2 above shows the block diagram of the JP18 architecture. 5.2 Product applications - Handheld GPS receiver applications - Automotive applications - Marine navigation applications - Aviation applications - Timing applications This confidential document is the property of FALCOM and may not be copied or circulated without permission. Page 12
JP18 FALCOM GPS RECEIVER VERSION 1.0.7 5.3 Technical specifications 5.3.1 Electrical Characteristics � GPS features: � Horizontal position accuracy: � Datum: � Sensitivity: � O EM single board 20 channel GPS receiver, L1 1575.42 MHz, C/A code 1,023 MHz chip rate. � GPS receiver with SiRFstarIII – GSC3LTf chip � Processor type ARM7/TDMI � A utonomous < 2.5 meters � SBAS
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