FALCOM JP18 GPS receiver - Hardware manual

JP18 FALCOM GPS RECEIVER VERSION 1.0.7
6 HARDWARE INTERFACE AND CONFIGURATION
SIGNALS
6.1 JP18 - QFN-Pin Configuration
Note the orientation of pins on the JP18 receiver. When viewing the back side
on the JP18 receiver, you will see a cut pad on the lower-right-corner. Given
this viewing orientation (see fig. 7), Pad 22 is on the right-bottom and Pad 1 is on
the bottom-right.
Figure 4: JP18 pin identification
PAD Name I/O Description Level
1 GPIO 0 I/O User defined GPIO 1.8 V
2 VRTC_REG_IN I Power for RTC and SRAM. It must be always connected to
the VCC pin.
3 ON/OFF I In the hardware revision "4d", this pin is internally pulled low
through a 47 kΩ resistor. If not used leave it open. For
detailed information about this pin, see description in chapter
6.2, page 22.
3.3 V – 5.5 V
4 VRF O Output RF-regulator 2.7 V; Imax = 10 mA
5 VANT I Power-supply for the active GPS antenna. Vin = 2.7V - 5V; Imax =20 mA
6 GND - Ground 0 V
7 RF_IN I RF-Input, L1, 1575,42 MHz 50 Ohms @ 1575,42 MHz
8 GND - Ground 0 V
1.2 V
9 WAKEUP O Regulator Power Down Output. Active low 1.2 V
10 TM O Time Mark Output (1 PPS) 1.8 V
11 RXA I RS232 line (receive data) 1.8 V
12 TXA O RS232 line (transmit data) 1.8 V
13 RES I System Reset Input. Connect to GND for RESET. 1.2 V
14 SPI_DI I SPI-Data-IN
15 SPI_DO O SPI-Data-OUT
Not supported in the current
1.8 V
16 SPI_CS O SPI-Chip-Select
software.
1.8 V
1.8 V
17 SPI_CLK I SPI-Clock 1.8 V
18 DATA 0 I Input at startup. See Table 1: 1.8 V
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