FALCOM JP18 GPS receiver - Hardware manual

JP18 FALCOM GPS RECEIVER VERSION 1.0.7
1 INTRODUCTION
1.1 General
This description is focussed on the GPS receiver of the FALCOM JP18 from
FALCOM.
The JP18 architecture is based on the SiRFstarIII core (GSC3LTf chipset), the
same industry-leading GPS DSP core design found all members of the GSC3
family, but implemented in leading-edge 90 nm fabrication process
technology, operating at 1.2V to provide superior performance and best-inclass
power consumption.
The new differentiating features that give the JP18 its unique identity are: the
new lower power SiRFstarIII-LT core, integrated 4 Mbits program ROM with ROM
patch memory, UART, and a new highly optimized 11 mm x 11 mm multi-chip
module with a height of 1.7 mm. The LNA is enabled and disables automatically
from the software to lower overall power consumption when the receiver is not
in use.
The single board solution offered in 22-pin (11 mm x 11 mm) QFN mounting
device is optimized for location applications requiring high performance in a
very small form factor - ideal for devices with limited on-board processing
power.
The JP18 concept builds perfect basis for the design of high-sensitive, lowpower,
compact and cost efficient state-of-the-art GPS enabled system
solutions for target platforms such as mobile phones, automotive systems,
portable computing devices, and embedded consumer devices. The FALCOM
JP18 is also designed to be entire products such as AVL tracking units,
handheld GPS.
1.2 Order options
Figure 1: The top (left) and bottom (right) views of the FALCOM JP18
Name Description
JP18 Packaged in a 22-pin package QFN mounting
Table 1: Ordering options
This confidential document is the property of FALCOM and may not be copied or circulated without permission.
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