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Tab Electronics Guide to Understanding Electricity ... - Sciences Club

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Digital <strong>Electronics</strong><br />

349<br />

Multivibra<strong>to</strong>rs<br />

Multivibra<strong>to</strong>rs are used extensively in digital electronics <strong>to</strong> provide clock<br />

signals (oscilla<strong>to</strong>rs), count and s<strong>to</strong>re data, and control timing sequences.<br />

They can be divided in<strong>to</strong> three major groups, or types: astable multivibra<strong>to</strong>rs<br />

(called clocks or oscilla<strong>to</strong>rs), bistable multivibra<strong>to</strong>rs (flip-flops), and<br />

monostable multivibra<strong>to</strong>rs (one-shots).<br />

You should already be familiar with astable multivibra<strong>to</strong>rs from our previous<br />

discussions regarding their use in sound circuits. The term astable<br />

means “not stable”; they cannot come <strong>to</strong> rest in either a high or low state.<br />

In other words, they oscillate. Because their outputs are in the form of a<br />

square wave, they are naturally suited <strong>to</strong> digital systems. IC forms of<br />

astable multivibra<strong>to</strong>rs are designed <strong>to</strong> operate at very high speeds.<br />

Three common examples of bistable multivibra<strong>to</strong>rs are illustrated in Fig.<br />

13-1. As the name suggests, bistable multivibra<strong>to</strong>rs have two stable states:<br />

“set” and “reset.” They are usually called “flip-flops” (F-Fs).<br />

Referring <strong>to</strong> Fig. 13-1, notice that each F-F has a “Q” and “NOT Q” output.<br />

The NOT Q output is always logically opposite of the Q output.<br />

When an F-F is “reset,” the Q output will be a logic 0, thus meaning that<br />

the NOT Q is a logical 1. If an F-F is “set,” the logical states of the Q and<br />

NOT Q will be reversed.<br />

The first F-F illustrated in Fig. 13-1 is a “set-reset (RS) F-F,” or RS flipflop.<br />

If a logical 1 is applied <strong>to</strong> the R (reset) input, the Q output goes <strong>to</strong><br />

logical 0. Similarly, if a logical 1 is applied <strong>to</strong> the S (set) input, the Q output<br />

will go <strong>to</strong> a logical 1. RS flip-flops have limited use in most digital<br />

systems. Their importance lies in their ability <strong>to</strong> latch, or remember, a<br />

logical status (if the logic levels <strong>to</strong> the RS inputs are not altered).<br />

The second type of F-F illustrated is the JK flip-flop. The JK inputs are<br />

“clocked inputs.” This means that the logical levels applied <strong>to</strong> the JK<br />

inputs have no effect without a coincidental pulse applied <strong>to</strong> the clock<br />

input. For example, if the K input is 1 and the J input is 0, the F-F will<br />

reset as soon as a clock pulse is applied <strong>to</strong> the clock input. If the K input<br />

changes <strong>to</strong> 0, and the J input goes <strong>to</strong> 1, the F-F will set as soon as (but<br />

not before) another pulse is received at the clock input.<br />

If both the J and K inputs are held at logical 1, a JK flip-flop<br />

becomes a <strong>to</strong>ggle F-F. The output, or Q status, of a <strong>to</strong>ggle F-F will change<br />

state every time the correct transitional change occurs at the clock input.<br />

Toggle F-F’s are designed <strong>to</strong> change state, or <strong>to</strong>ggle, on either the “leading<br />

edge” or “trailing edge” of input clock pulses. For example, if a <strong>to</strong>ggle F-F<br />

is specified <strong>to</strong> <strong>to</strong>ggle on the trailing edge of the input clock pulses, a

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