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Fast Models Reference Manual - ARM Information Center

Fast Models Reference Manual - ARM Information Center

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Processor ComponentsTable 4-3 <strong>ARM</strong>CortexA15xnCT individual processor parameters (continued)Parameter Description TypeAllowedValueDefaultValuesemihosting-heap_limit Virtual address of top of heap. Integer 0x00000000-0xFFFFFFFF0x0F000000semihosting-stack_baseVirtual address of base of descendingstack.Integer 0x00000000-0xFFFFFFFF0x10000000semihosting-stack_limit Virtual address of stack limit. Integer 0x00000000-0xFFFFFFFF0x0F000000vfp-enable_at_reset bvfp-present aEnable coprocessor access and VFP atreset.Set whether CT model has been builtwith VFP support.Boolean true or false falseBoolean true or false truea. The ase-present and vfp-present parameters configure the synthesis options for the Cortex-A15 model. The options are:vfp present and ase presentNEON and VFPv4-D32 supported.vfp present and ase not presentVFPv4-D16 supported.vfp not present and ase presentIllegal. Forces vfp-present to true so model has NEON and VFPv4-D32 support.vfp not present and ase not presentModel has neither NEON nor VFPv4-D32 support.b. This is a model-specific behavior with no hardware equivalent.4.2.4 RegistersThe <strong>ARM</strong>CortexA15xnCT component provides the registers specified by the technicalreference manual for the Cortex-A15 processor with the following exceptions:• coprocessor 14 registers are not implemented• integration and test registers are not implemented.4.2.5 CachesThe <strong>ARM</strong>CortexA15xnCT component implements L1 and L2 cache as architecturally defined.4.2.6 Debug FeaturesThe <strong>ARM</strong>CortexA15xnCT component exports a CADI debug interface.RegistersAll processor, VFP, CP14 and CP15 registers, apart from performance counter registers, arevisible in the debugger. All CP14 debug registers are implemented. See the processor technicalreference manual for a detailed description of available registers.BreakpointsThere is direct support for:• single address unconditional instruction breakpoints• unconditional instruction address range breakpoints• single address unconditional data breakpoints.<strong>ARM</strong> DUI 0423N Copyright © 2008-2012 <strong>ARM</strong>. All rights reserved. 4-8ID120712Non-Confidential

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