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Fast Models Reference Manual - ARM Information Center

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Processor ComponentsTable 4-7 <strong>ARM</strong>CortexA9UPCT ports (continued)Name Port protocol Type Descriptionstandbywfi[0] Signal master Indicates if a processor is in WFI state.teinit[0] Signal slave Initialize to take exceptions in T32 state after a reset.ticks[0] InstructionCount master Processor instruction count for visualization.vinithi[0] Signal slave Initialize with high vectors enabled after a reset.4.4.2 Additional protocolsThe <strong>ARM</strong>CortexA9UPCT component has two additional protocols. See Additional protocolson page 4-109.4.4.3 ParametersTable 4-8 lists the parameters set at the processor level for the <strong>ARM</strong>CortexA9UPCTcomponent.Table 4-8 <strong>ARM</strong>CortexA9UPCT parameters aParameter Description TypeAllowedvalueDefaultvalueCLUSTER_ID Processor cluster ID value. Integer 0-15 0device-accurate-tlbdcache-state_modelledicache-state_modelledSpecify whether all TLBsare modeled.Set whether D-cache hasstateful implementation.Set whether I-cache hasstateful implementation.Boolean true or false false bBoolean true or false falseBoolean true or false falsea. For the <strong>ARM</strong>CortexA9UP processor, the instance name for the processor consists of the normal instancename (in the provided examples, coretile.core) with a suffix of cpu0. In the example Cortex-A9 platform theinstance name is coretile.core.cpu0.b. Specifying false models enables modeling a different number of TLBs if this improves simulationperformance. The simulation is architecturally accurate, but not device accurate. Architectural accuracy isalmost always sufficient. Specify true if device accuracy is required.Table 4-9 provides a description of the processor configuration parameters for the<strong>ARM</strong>CortexA9UPCT component.Table 4-9 <strong>ARM</strong>CortexA9UPCT individual processor parametersParameter Description TypeAllowedvalueDefaultvalueCFGEND Initialize to BE8 endianness. Boolean true or false falseCFGNMFICP15SDISABLEEnable nonmaskable FIQ interruptson startup.Initialize to disable access to someCP15 registers.Boolean true or false falseBoolean true or false false<strong>ARM</strong> DUI 0423N Copyright © 2008-2012 <strong>ARM</strong>. All rights reserved. 4-18ID120712Non-Confidential

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