Fast Models Reference Manual - ARM Information Center

Processor Components4.3.10 Differences between the CT model and RTL implementationsThe ARMCortexA9MPxnCT component differs from the corresponding revision of the ARMCortex-A9 RTL implementation in the following ways:• The ARMCortexA9MPxnCT does not implement address filtering within the SCU. Theenable bit for this feature is ignored.• The GIC does not respect the CFGSDISABLE signal. This leads to some registers beingaccessible when they must not be.• The SCU enable bit is ignored. The SCU is always enabled.• The SCU ignores the invalidate all register.• The Broadcast TLB or cache operations in the ARMCortexA9MPxnCT model do notcause other processors in the cluster that are asleep because of WFI to wake up.• The RR bit in the SCTLR is ignored.• The Power Control Register in the system control coprocessor is implemented but writingto it does not change the behavior of the model.• The model cannot be configured with a 128-entry TLB.• When modeling the SCU, coherency operations are represented by a memory writefollowed by a read to refill from memory, rather than using cache-to-cache transfers.ARM DUI 0423N Copyright © 2008-2012 ARM. All rights reserved. 4-16ID120712Non-Confidential