Full-Custom Analog IC Design using Cadence DFII Virtuoso/Assura

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4. CREATING THE TEST BENCH Create a new schematic view in your library (VLSITP) named DiffPair2_tb. Instantiate the symbol of the ADC2 schematic that you have already generated inprevious section into the new schematic entry window. Then complete the schematicas shown in Figure 6.Figure 8 - The schematic of the test bench for the ADC2 For the DC source use vdc component from analogLib library, and set the DC voltageproperty to 3.3V. For the load capacitors shown in the schematic, use the cap element from analogLib,and edit the capacitance property to enter the provided value in the schematic (50 fF). For the ground symbol, use gnd cell symbol view from analogLib library. gnd symbol12/23
will provide the zero reference voltage level for your simulation. Use Add→Wire Name or pres “l” to place labels accordingly on to input/output signalsas shown in Figure 86. Check and Save your design.Parameter ValueDC voltage: V2 vdc VDC Voltage: V0 3.3 VDC Voltage: V1 0.0 VDC Current: I0 100u ATable. 1. Parameters for the inputs.Checkpoint Please call an assistant and show him/her that you have reachedthis point before working on further stepsVisaSIMULATING THE PERFORMANCE OF THE DESIGN For opening of the simulation environment click on Tools→Analog Environment onthe very left upper corner of the schematic window. Analog Design Environmentwindow will pop-up, Fig. 9.Figure 9- The Analog Design Environment (ADE) Window13/23
Page 1 and 2: LABORATOIRE DE SYSTEMES MICROELECTR
Page 3 and 4: Figure 1 - The CIW (Command Interpr
Page 5 and 6: Creating an new library Using the l
Page 7 and 8: Choose Add→Instance from the menu
Page 9 and 10: then drag the inverter to a new loc
Page 11: When you are done, Check and Save y
Page 15 and 16: Figure 10- DC simulation setupWorki
Page 17 and 18: All available layers and their rela
Page 19 and 20: step involved design rules are list
Page 21 and 22: Figure 16 - Example for error in la
Page 23: Figure 20- Set up for post-layout s

Full-Custom Analog IC Design using Cadence DFII Virtuoso/Assura

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