Full-Custom Analog IC Design using Cadence DFII Virtuoso/Assura

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Once you have a DRC clean layout, run the LVS tool (Assura -> LVS). LVS tool is tocompare the netlist of your main schematic to the netlist which is extracted from layout.You should find the reason for each mismatch report and try to solve it on your layout.Figure 18- LVS windows pops up after running LVSFigure 19- Typical LVS error report page Once your LVS is clean, create an extracted view (Assura -> RCX) of the layout. In thisway the netlist extracted from your layout will be created. Now, you can re-run yoursimulation with the new netlist includes parasitic effects raised in layout. Then run a post layout simulation using the same simulation environment that you usedfor the pre layout simulation. For this purpose you just need to change the set-up of yourADE. In ADE just add “av_extracted” in Setup -> Environment menu as the first itemon the switch view list:22/23
Figure 20- Set up for post-layout simulationCheckpoint Please call an assistant and show him/her that you have reachedthis point before working on further stepsVisa23/23
Page 1 and 2: LABORATOIRE DE SYSTEMES MICROELECTR
Page 3 and 4: Figure 1 - The CIW (Command Interpr
Page 5 and 6: Creating an new library Using the l
Page 7 and 8: Choose Add→Instance from the menu
Page 9 and 10: then drag the inverter to a new loc
Page 11 and 12: When you are done, Check and Save y
Page 13 and 14: will provide the zero reference vol
Page 15 and 16: Figure 10- DC simulation setupWorki
Page 17 and 18: All available layers and their rela
Page 19 and 20: step involved design rules are list
Page 21: Figure 16 - Example for error in la

Full-Custom Analog IC Design using Cadence DFII Virtuoso/Assura

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