Full-Custom Analog IC Design using Cadence DFII Virtuoso/Assura

Figure 15 – Assura set-upAfter DRC finishes in case there are errors the Error Layer Window will pop-up (example inFigure 16). To correct the error do the following Select error in Error Layer Window. The error will be marked in the Layout Editor. Read description and if necessary find the error according to Rule code in DRM. Correct the error. Repeat the procedure until all the errors are corrected. Do a Design→Save or press “F2”. Use Assura→Close Run from the menu to stop current check. Repeat DRC procedure until you get the message “No DRC errors found” (Figure 17).20/23