Full-Custom Analog IC Design using Cadence DFII Virtuoso/Assura

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Setting up Variables and Outputs Copy your design using Variables→Copy from Cellview menu command. The variables will appear in the “Design Variables” pane (Figure 10). Double click on each of the variables available in the list and set their values to nominalvalue (in this case vdc = 1.6 V). Use Outputs→To be Plotted/Select on Schematic command in the Analog DesignEnvironment. Select vi, b0 and b1 nets by clicking on them sequentially (by this all selected nets willbe highlighted in different colours). Also, select the vdd pin of your ADC2 to monitor the current consumption of the design(a coloured circle will appear around the selected pin). All selected signals should appear in the “Outputs” pane of the Analog DesignEnvironment. The final setup for the DC simulation should look like the one shown inFigure 10.DC ANALYSISSetup a DC analysis in order to simulate the voltage transfer curve (VTC) of the NAND2 gate.This analysis allows you to verify the DC characteristics of the design, like switching threshold,noise margins, logic levels, etc. Use Analysis→Choose in order to select the type of the simulation you would like torun. In the pop-up window, edit the necessary properties as shown in Figure 10. Use Session→Save State to save your simulation setup so you can reload it at a futuretime To run simulation use Simulation→Netlist and Run command from the Analog DesignEnvironment window.This command will generate the netlist of your design automatically and run the specified simulationsetup on this netlist. The progress of the simulation is displayed on the screen as a text window. Assoon as the simulation is completed, a “Waveform Window” appears with all the selected signalsdisplayed in a single graph.14/23
Figure 10- DC simulation setupWorking with the “Waveform Window” To split the Waveform window view into multiple graphs use Axes→To Stripcommand. To combine the waveforms on one graph drag and drop them. The final waveformshould look like the one presented in Figure 11 (combine only voltage curves). To zoom, use the Zoom menu or press “z” X/Y coordinates pointed by the mouse are displayed on the top of the window, near thetitle bar.Figure out the switching threshold from the waveforms. Now quit the Analog Design Environment by simply selecting Session→Quit.15/23
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Page 3 and 4: Figure 1 - The CIW (Command Interpr
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Page 7 and 8: Choose Add→Instance from the menu
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Page 11 and 12: When you are done, Check and Save y
Page 13: will provide the zero reference vol
Page 17 and 18: All available layers and their rela
Page 19 and 20: step involved design rules are list
Page 21 and 22: Figure 16 - Example for error in la
Page 23: Figure 20- Set up for post-layout s

Full-Custom Analog IC Design using Cadence DFII Virtuoso/Assura

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