Manual - Xpress Platforms

MS-7640▶tRCThe row cycle time determines the minimum number of clock cycles a memory rowtakes to complete a full cycle, from row activation up to the precharging of the activerow.▶tWRMinimum time interval between end of write data burst and the start of a prechargecommand. Allows sense amplifiers to restore data to cells.▶tRRDSpecifies the active-to-active delay of different banks.▶tWTRMinimum time interval between the end of write data burst and the start of a columnreadcommand. It allows I/O gating to overdrive sense amplifiers before readcommand starts.▶tRFCThis setting determines the time RFC takes to read from and write to a memorycell.▶Advanced Channel 1/ 2 Timing ConfigurationPress to enter the sub-menu. And you can set the advanced memory timingfor each channel.Chapter 3▶tRWTT02/ tWRRD2/ tWRWR2/ tRDRD2These items is used to set the memory timings for memory channel 1/ 2.▶DCT Unganged ModeThis feature is used to Integrate two 64-bit DCTs into a 128-bit interface.▶Bank InterleavingBank Interleaving is an important parameter for improving overclocking capability ofmemory. It allows system to access multiple banks simultaneously.▶HT Link SpeedThis item allows you to set the Hyper-Transport Link speed. Setting to [Auto], the systemwill detect the HT link speed automatically.▶Adjusted HT Link FrequencyIt shows the adjusted HT Link frequency. Read-only.▶CPU Core ControlThis item allows you to select the number of active processor cores.▶UnlockCPU CoreThis item is used to unlock the CPU core. Please refer to the procedures below for CPUcore unlocked in BIOS setup.3-13