LMX3160 Single Chip Radio Transceiver

A plot of the magnitude and phase of G(s)H(s) for a stableloop is shown in Figure 4 with a solid trace The parameterw p shows the amount of phase margin that exists at thepoint the gain drops below zero (the cutoff frequency wp ofthe loop) In a critically damped system the amount ofphase margin would be approximately 45If we were now to redefine the cut off frequency 0 p asdouble the frequency which gave us our original loop bandwidthwp the loop response time would be approximatelyhalved Because the filter attenuation at the comparison frequencyalso diminishes the spurs would have increased byapproximately 6 dB In the proposed FastLock scheme thehigher spur levels and wider loop filter conditions would existonly during the initial lock-on phasejust long enough toreap the benefits of locking faster The objective would beto open up the loop bandwidth but not introduce any additionalcomplications or compromises related to our originaldesign criteria We would ideally like to momentarily shift thecurve of Figure 4 over to a different cutoff frequency illustratedby the dotted line without affecting the relative openloop gain and phase relationships To maintain the samegainphase relationship at twice the original cutoff frequencyother terms in the gain and phase equations 4 and 5 willhave to compensate by the corresponding ‘‘10’’ or ‘‘10 2 ’’factor Examination of equations 3 and 5 indicates thedamping resistor variable R2 could be chosen to compensatethe ‘‘0’’ terms for the phase margin This implies thatanother resistor of equal value to R2 will need to beswitched in parallel with R2 during the initial lock period Wemust also insure that the magnitude of the open loop gainH(s)G(s) is equal to zero at 0 p e 2 0 p K vco K w Northenet product of these terms can be changed by a factor of 4to counteract the 0 2 term present in the denominator ofEquation 3 The Kw term was chosen to complete the transformationbecause it can readily be switched between 1Xand 4X values This is accomplished by increasing thecharge pump output current from 15 mA in the standardmode to 6 mA in FastLockFastLock Circuit ImplementationA diagram of the FastLock scheme as implemented in NationalSemiconductors LMX3160 is shown in Figure 5 Whena new frequency is loaded the charge pump circuit receivesan input to deliver 4 times the normal current per unit phaseerror while an open drain NMOS on chip device switches ina second R2 resistor element to ground The user calculatesthe loop filter component values for the normal steadystate considerations The device configuration ensures thatas long as a second identical damping resistor is wired inappropriately the loop will lock faster without any additionalstability considerations to account for Once locked on thecorrect frequency the PLL will then return to standard lownoise operation This transition does not affect the chargeon the loop filter capacitors and is enacted synchronouswith the charge pump output This creates a nearly seamlesschange between FastLock and standard modeFigure 4 Open Loop Response Bode PlotTLW12493–11FIGURE 5 FastLock PLL ArchitectureTLW12493–1215