LMX3160 Single Chip Radio Transceiver

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Electrical Characteristics The following specifications are guaranteed over the recommended operating conditionsunless otherwise specified (Continued)Symbol Parameter Conditions Min Typ Max UnitFREQUENCY SYNTHESIZERV OSC Oscillator Sensitivity 05 10 V PPI Do-source Charge Pump Output Current V do e V P 2 I cpo e LOW (Note 4) b15 mAI Do-sink V do e V P 2 I cpo e LOW (Note 4) 15 mAI Do-source V do e V P 2 I cpo e HIGH (Note 4) b60 mAI Do-sink V do e V P 2 I cpo e HIGH (Note 4) 60 mAI Do-Tri05 s V dos V P b05T A e 25Cb10 01 10 nAV OH High-Level Output Voltage I OH eb10 mA V CC b04 VV OL Low-Level Output Voltage I OL e 10 mA 04 VV IH High-Level Input Voltage V CC b08 VV IL Low-Level Input Voltage 08 VI IN Input Current GND k V INk V CC b10 10 mAt CS Data to Clock Set Up Time See Data Input Timing 50 nst CH Data to Clock Hold Time See Data Input Timing 10 nst CWH Clock Pulse Width High See Data Input Timing 50 nst CWL Clock Pulse Width Low See Data Input Timing 50 nst ES Clock to Load Enable Set Up Time See Data Input Timing 50 nst EW Load Enable Pulse Width See Data Input Timing 50 nsDC COMPENSATION SAMPLE AND HOLD CIRCUITV OS Input Offset Voltage 3 mVV IO InputOutput Voltage Swing Centered at 15V 10 V PPR SH Sample and Hold Resistor 224 336 XD V Threshold Input Voltage Droop C hold e 2700 pF 1 10 mVmsNote 1 This includes 5 mA current sourced from the Rx V REG pin for the external receive LNA as shown in the application diagramNote 2 This includes 5 mA current sourced from the Tx V REG pin for the external transmit buffer used before the power amplifier as shown in the applicationdiagramNote 3 Measured at the output of external gain stageNote 4 See programmable modes for I cpo description6
Serial Data Input TimingTLW12493–3Notes Parenthesis data indicates programmable reference divider dataData shifted into register on clock rising edgeData is shifted in MSB firstTest Conditions The Serial Data Input Timing is tested using a symmetrical waveform around V CC 2 The test waveform has an edge rate of 06Vns withamplitudes of 22V V CC e 30V and 26V V CC e 55VPLL Functional DescriptionThe simplified block diagram below shows the 20-bit data register 18-bit F latch 12 bit N counter and 6 bit R counterTLW12493–47
Page 1 and 2: LMX3160 Single Chip Radio Transceiv
Page 3 and 4: LMX3160 Pin Diagram (Continued)Pin
Page 5: Electrical Characteristics The foll
Page 9 and 10: 6-Bit Programmable Counter Divide R
Page 11 and 12: Programmable ModesSeveral modes of
Page 13 and 14: Typical Application Block DiagramNo
Page 15 and 16: A plot of the magnitude and phase o

LMX3160 Single Chip Radio Transceiver

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