Xilinx UG198 Virtex-5 FPGA RocketIO GTX Transceiver, User Guide

OverviewGTX transceivers are placed as dual transceiver GTX_DUAL tiles in Virtex-5 FXT and TXTdevices. This configuration allows two transceivers to share a single PLL with the TX andRX functions of both, reducing size and power consumption.Figure 1-1 shows GTX_DUAL tile placement in an example Virtex-5 device(XC5VFX100T). All GTX_DUAL tiles form a single GTX_DUAL column on the right side ofan FXT device as shown in Figure 1-1. TXT devices have one GTX_DUAL column on theleft side of the device and one column on the right side of the device as shown inFigure 1-2. The embedded processor blocks in Virtex-5 FXT devices contain aPowerPC® 440 processor along with several additional modules.Additional information on the functional blocks in Figure 1-1 is available in the followinglocations:• The Embedded Processor Block for Virtex-5 FPGAs Reference Guide [Ref 2] provides moreinformation on the embedded processor block for Virtex-5 FPGAs.• Chapter 8, “Cyclic Redundancy Check,” provides more details on the CRC blocks inFigure 1-1.• UG191, Virtex-5 FPGA Configuration Guide provides more information on theConfiguration and Clock, CMT, and I/O blocks.• UG194, Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide provides detailedinformation on the Ethernet MAC.• UG197, Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express Designsprovides detailed information on PCI Express compliance.RocketIO GTX Transceiver User Guide www.xilinx.com 25UG198 (v3.0) October 30, 2009